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Round 13 — Combined answers (Gemini · GPT · Claude)

Contents

• 0. Resume probe
  • M13Q1 · "When you did your three post-freeze gate-level ECOs and when…
• Part A — Rapid-fire Q and A (0:05–0:20)
  • M13Q2 · A1. What is the difference between a standard D-flop and a…
  • M13Q3 · A2. Distinguish scan_mode (test_mode / tm) from scan_en (SE).…
  • M13Q4 · A3. What happens during scan shift if an internal flop drives…
  • M13Q5 · A4. Look at an Integrated Clock Gating (ICG) cell: why does it…
  • M13Q6 · A5. Stuck-at fault model vs. Transition-delay (at-speed) fault…
  • M13Q7 · A6. Launch-on-Capture (LOC / broadside) vs. Launch-on-Shift…
  • M13Q8 · A7. What is an On-Chip Clock Controller (OCC / OPCC) in…
  • M13Q9 · A8. A scan chain contains flops from two clock domains (clk_a…
  • M13Q10 · A9. What is Scan Compression (EDT / DFTMAX compression)? Why…
  • M13Q11 · A10. You used reset-less datapath flops in your design to save…
  • M13Q12 · A11. What is "shadow logic" around a non-scan macro (like an…
  • M13Q13 · A12. Why are multicycle paths (set_multicycle_path) and false…
  • M13Q14 · A13. During scan shift, thousands of flops toggle…
  • M13Q15 · A14. When you hand-edit a gate-level netlist for a post-freeze…
• Part B — Deep dive: DFT DRC Audit, Fixes and Coverage Recovery…
  • M13Q16 · B1. (15 min) Identify all 6 DFT DRC / ATPG issues
  • M13Q17 · B2. (15 min) Rewrite the RTL to be 100% DFT-clean
  • M13Q18 · B3. (5 min) At-Speed SDC Exceptions
• Part C — Your questions (0:55–1:00)
  • M13Q19 · C1. Questions for the interviewer
• Additional notes
  • Notes. Material not tied to a question

0. Resume probe

M13Q1 · "When you did your three post-freeze gate-level ECOs and when you redesigned blocks at NXP, what DFT checks did you have to pass or be careful not to break?"

Gemini Answer

• Answer:
  • During Post-Freeze Gate-Level ECOs:
    1. Scan-Chain Integrity (SI -> SO path): Never break an existing scan chain (SDFF .SI and .SE connections) or introduce a non-scan DFF into a synthesized netlist. If an ECO only modifies combinational logic (like my AOI21 abort patch), verify scan_en == 0 equivalence in LEC and notify DFT to top-up ATPG patterns for the modified logic cone. If a spare SDFF is consumed, verify its clock domain matches the chain segment (or sits behind a lockup latch) and its async reset is scan-controllable.
  • During Block RTL Design & Redesigns:
    1. Clean SpyGlass DFT DRC: Ensure all asynchronous resets and gated/muxed clocks have scan_mode bypass muxes so ATPG has 100% pin controllability during shift.
    2. ICG TE Hookup & X-Bounding: Ensure all clock gates hook up TE and any non-scan/analog/custom boundary inputs are X-bounded so scan compression doesn't lose fault coverage.

GPT Answer

"I performed three post-freeze gate-level ECOs with equivalence checks and own RTL releases/backend coordination. I would explain the actual scan/ATPG signoff involved in those changes, but the resume does not list my DFT ownership or coverage results. I would not claim to have owned the DFT architecture."

Claude Answer

Template: "For the hand ECOs: no new flops, so no chain change — but I still re-ran the DFT
DRC on the patched netlist, confirmed scan_en was constrained in LEC, and had ATPG
regenerated because the changed cone changes the fault list; the one time a spare flop was
in play, the rule was 'pre-stitched or don't use it'. For the redesigns (NDBPS lookup,
re-pipelined length path, TSF/beacon absorption): every new flop has a scan-controllable
clock, no generated or gated clocks outside ICG cells, resets only from the reset tree with
a scan_mode bypass, no latches, reset-less datapath flops accepted because they're on
chains, and the baseband-interface inputs X-bounded so compression patterns stay clean. I
ran SpyGlass DFT on the block before hand-off and attached the report to the release."

Part A — Rapid-fire Q and A (0:05–0:20)

M13Q2 · A1. What is the difference between a standard D-flop and a multiplexed-D scan flop (SDFF)? Draw or state its pins (D, SI, SE, CK, RN, Q) and the Boolean equation of what gets clocked in.

Gemini Answer

• Pins: D (functional data), SI (scan chain input from previous flop's Q), SE (scan enable), CK (clock), RN (active-low async reset), Q (output / SO).
• Next-state Boolean equation (when RN == 1):$$Q_{\text{next}}=\text{SE}?\text{SI}:D=(\text{SE}\cdot \text{SI})+(\overline{\text{SE}}\cdot D)$$

GPT Answer

A muxed-D scan flop clocks SE ? SI : D into Q on its active CK edge, unless its active-low RN resets it. SI/SE add controllable scan loading while D supports functional capture. Exact reset priority and cell pins come from the library.

Claude Answer

An SDFF adds a 2:1 mux in front of D: D_in = SE ? SI : D. Pins: D, SI, SE,
CK, RN (async reset), Q (doubles as SO for the next flop). Clocked in: SE·SI + ~SE·D.

M13Q3 · A2. Distinguish scan_mode (test_mode / tm) from scan_en (SE). Which one toggles during an ATPG pattern between shift and capture, and which one stays static (1'b1) for the entire test?

Gemini Answer

• scan_mode: Static 1'b1 throughout the entire ATPG test (both shift and capture phases). Used to force reset muxes, clock-tree bypass muxes, and black-box X-bounding muxes into test-controllable states.
• scan_en (SE): Dynamic control signal that is 1'b1 during scan shift (connecting all flops into serial shift registers SI -> Q) and drops to 1'b0 during the functional capture cycle(s) so flops sample the combinational logic cone on D.

GPT Answer

scan_mode is normally static for the test session; scan_en selects shift versus functional capture and changes within a pattern. At-speed timing requirements apply to that transition, especially LOS. Other test modes such as MBIST/OCC may have separate controls.

Claude Answer

scan_mode/tm is static 1 for the whole test: selects test clocks, bypasses
generated clocks and internal resets, enables X-bounding muxes. scan_en/SE toggles per
pattern: 1 during shift, 0 for the capture cycle(s).

M13Q4 · A3. What happens during scan shift if an internal flop drives the asynchronous reset (rst_n) of another flop without a scan_mode mux? What is the exact DFT DRC violation called, and how do you fix it?

Gemini Answer

• What happens: As arbitrary test vectors (10110...) shift serially through the scan chain, the flop driving rst_n toggles randomly on every shift clock, asynchronously wiping downstream scan flops to 0 mid-shift and corrupting the scan chain!
• Exact DFT DRC violation: Uncontrollable / Internally-Driven Asynchronous Set/Reset Violation (SpyGlass DFT_async_reset / TetraMAX C3/C4 clock/reset rule).
• Fix: Add a 2:1 scan_mode bypass mux right on the reset line:

  assign sub_rst_n = scan_mode ? top_scan_rst_n : func_internal_rst_n;
  

GPT Answer

A shifting flop can asynchronously reset downstream scan state, destroying loaded patterns and causing uncontrollable/internal asynchronous-reset DRC failures. Rule IDs are tool/deck-specific. Select a primary test reset while scan mode is active, with static/glitch-safe mode entry, rather than allowing the shifting functional reset source to control RN.

Claude Answer

As patterns shift through the driving flop, its Q toggles and asynchronously resets
downstream flops mid-shift, destroying chain contents. DRC: uncontrollable/internally
generated asynchronous reset. Fix: rst_mux = scan_mode ? test_rst_n : func_rst_n so the
reset is a primary pin during test.

M13Q5 · A4. Look at an Integrated Clock Gating (ICG) cell: why does it have both an EN pin and a TE (Test Enable) pin? Should TE be connected to scan_en, scan_mode, or driven by the DFT controller, and why does that choice affect at-speed capture power and fault coverage?

Gemini Answer

• Why TE exists inside the ICG (GCLK = CLK & Latch(EN | TE)): During scan shift (SE = 1), every flip-flop in the scan chain must receive a clock pulse on every shift cycle regardless of what value is currently sitting in the functional EN logic.
• Why TE = scan_en beats TE = scan_mode:
  • If TE = scan_mode (always 1), the ICG is forced open during both shift AND capture—meaning the functional EN pin of the ICG is untestable (0% fault coverage on the clock-gating enable cone!) and 100% of chip flops toggle simultaneously during at-speed capture, causing massive IR drop!
  • Connecting TE = scan_en (or scan_en | cgc_override) forces all ICGs ON during shift (SE = 1), and lets the functional EN cone control the ICG during capture (SE = 0)—testing the EN logic for faults and keeping capture switching power realistic!

GPT Answer

EN controls functional gating; TE allows test clock access. Use the DFT methodology's shift/capture controls: often force open during shift and selectively enable capture. Tying TE permanently to scan_mode may over-toggle capture; tying it only to scan_en may block required capture clocks. The DFT/OCC controller must define the policy.

Claude Answer

EN is the functional enable through the latch; TE forces the clock on
regardless of EN. Connect TE = scan_en: all clocks run during shift so every chain
shifts, and during capture (SE = 0) the functional EN controls the ICG, which tests the
enable logic itself and keeps capture power close to functional. TE = scan_mode would run
every clock in capture: higher IR drop and the ICG enable cone untested.

M13Q6 · A5. Stuck-at fault model vs. Transition-delay (at-speed) fault model: what physical silicon defects does each catch, and how many capture clock pulses does an at-speed test require?

Gemini Answer

• Stuck-At (SA0 / SA1): Models a hard short to $V_{SS}$ or $V_{DD}$ (or open wire). Tested at slow clock speed (~20–50 MHz) with 1 capture clock pulse.
• Transition-Delay (Slow-to-Rise / Slow-to-Fall): Models resistive vias, weak transistors, or crosstalk that work at 20 MHz but fail to complete a $0\to 1$ or $1\to 0$ transition within one functional clock period (e.g., $1.56\text{ ns}$ at 640 MHz). Requires 2 at-speed clock pulses in the capture window (Launch edge + Capture edge).

GPT Answer

Stuck-at models a node permanently 0/1; transition testing targets slow-to-rise/fall defects with a launch and an at-speed observation. LOC usually uses two functional capture pulses, launch then capture; LOS launches on the last shift edge and uses a following capture edge. More pulses may be used by specific ATPG schemes.

Claude Answer

Stuck-at: a node tied permanently to 0/1 (opens, shorts to rails); one capture pulse
at slow tester speed. Transition delay: resistive vias, weak transistors, slow-to-rise/fall;
two pulses, launch and capture, separated by the functional period (1.56 ns at 640 MHz).

M13Q7 · A6. Launch-on-Capture (LOC / broadside) vs. Launch-on-Shift (LOS): how does each launch the transition at the start of the at-speed window, and why is LOS rarely used without special physical design support?

Gemini Answer

• Launch-on-Capture (LOC / Broadside):
  1. Shift in pattern ($N$ slow clocks with SE = 1).
  2. Drop SE = 0 and wait for SE to settle across the chip.
  3. Pulse Launch clock (SE = 0, functional logic launches transitions) followed $1.56\text{ ns}$ later by Capture clock (SE = 0).
  4. Raise SE = 1 and shift out.
• Launch-on-Shift (LOS): Uses the final shift clock edge (SE = 1) as the Launch edge, which requires SE to transition from 1 to 0 across 200,000 flip-flops in less than one 640 MHz clock period ($<1.56\text{ ns}$) before the Capture edge! Because routing SE as a full-speed balanced clock tree is expensive in area/power, LOC is the industry standard.

GPT Answer

LOC launches by functional evolution from a scanned state. LOS launches with the final shift operation; scan_en must switch with tight at-speed timing across the scan population, requiring specific timing/physical support.

Claude Answer

LOC: shift in state, drop SE, pulse launch (functional logic creates the
transition), pulse capture at speed. LOS: the last shift pulse is the launch and SE must
fall from 1 to 0 across every flop within one functional period, which makes SE a
clock-quality tree; rarely worth it.

M13Q8 · A7. What is an On-Chip Clock Controller (OCC / OPCC) in at-speed testing? Why can the tester not simply toggle the chip's external scan clock pin at 640 MHz during the capture phase?

Gemini Answer

• What it is: A small FSM inside the clock generation block that muxes between the slow external ATE tester clock (scan_clk, ~25 MHz) during scan shift and the fast on-chip PLL clock (pll_clk, 640 MHz) during the capture window.
• Why ATE cannot drive 640 MHz directly: Package pins, board traces, and tester pogo pins cannot cleanly transmit sub-nanosecond 640 MHz clocks without severe attenuation and skew; the OCC gates out an exact programmable 2-pulse burst (Launch + Capture) from the internal PLL when SE drops low.

GPT Answer

OCC selects/controls slow shift versus PLL-derived capture pulses and generates a defined glitch-free burst. A tester may not supply a sufficiently precise at-speed clock through the normal scan-pin/distribution path; internal clocks provide controlled phase/skew and domain sequencing.

Claude Answer

A controller that uses the on-chip PLL to emit a programmable burst of 2–3
at-speed pulses in capture and passes the slow ATE clock during shift. Tester pins and
package traces can't deliver clean 640 MHz edges, so the chip generates them.

M13Q9 · A8. A scan chain contains flops from two clock domains (clk_a and clk_b), or mixes posedge and negedge flops. What hold hazard occurs during scan shift, and what cell does the tool insert to prevent it?

Gemini Answer

• Hold hazard during shift: If Flop $A$ (in clk_1) shifts into Flop $B$ (in clk_2) where clk_2 has later clock-tree insertion delay than clk_1, Flop $A$'s output changes before Flop $B$ samples it on the same shift edge—causing a scan-shift hold violation that breaks the entire chain!
• Fixes:
  1. Place negedge flops before posedge flops in the chain (half-cycle margin).
  2. Insert a Lockup Latch (an active-low transparent latch clocked by the launching domain clk_1 when shifting from posedge clk_1 to posedge clk_2) at every clock-domain boundary in the scan chain, adding a full half-clock-period ($T_{\text{shift}}/2\approx 20\text{ ns}$) of hold margin!

GPT Answer

Shift-clock skew or mixed active edges can let data race into the next scan cell, violating hold. Lockup latches/flops and appropriate edge/domain stitching absorb that skew. They do not replace functional CDC structures.

Claude Answer

Different clock arrival or a negedge→posedge hop makes Q→SI a near-zero-delay path:
hold violation during shift. Tool orders negedge flops before posedge ones and inserts a
lock-up latch (opposite-phase transparent) at each domain boundary in the chain.

M13Q10 · A9. What is Scan Compression (EDT / DFTMAX compression)? Why does a single X (unknown value) entering the scan chain ruin a compressed scan pattern, and where do Xs come from in RTL?

Gemini Answer

• What it is: A decompressor expands $M$ external scan_in pins (e.g., 4 pins) into $K$ short internal scan chains (e.g., 200 chains), and an XOR compactor tree compresses the 200 internal scan_out chains back down to 4 external scan_out pins—cutting tester time and pattern memory by $50\times$.
• Why Xs break it: In an XOR tree, 1'bX ^ 1'b0 ^ 1'b1 == 1'bX! A single unknown (X) captured into one flop of Chain #17 propagates into the XOR compactor and blinds the tester to the outputs of all other chains sharing that XOR phase (requiring costly X-masking patterns that inflate test time and drop coverage).
• Sources of Xs in RTL: Un-bypassed SRAMs/ROMs, analog/PHY black-box inputs, un-constrained false/multicycle paths, and CDC crossings if both clocks pulse in capture.

GPT Answer

Compression expands a few tester inputs into scan chains and compacts responses. An unmasked X can contaminate many compacted observations; it does not necessarily ruin every bit of every pattern. Sources include analog/memory black boxes, uncontrolled resets/clocks and uninitialized non-scan state. Bound/mask X sources narrowly and retain observability.

Claude Answer

A decompressor expands a few scan-in pins into many short chains; an XOR compactor
folds the outputs. X ^ anything = X, so one X masks every fault observed through that
compactor slice. Xs come from uninitialised SRAMs, analog/black-box inputs, un-constrained
false/multicycle paths, CDC crossings, bus contention.

M13Q11 · A10. You used reset-less datapath flops in your design to save area/power. Does that hurt scan testing? Why or why not?

Gemini Answer

• No! During scan shift (SE = 1), every scan flop (SDFF) loads its state serially through its SI pin—it does not use its reset pin to initialize for ATPG! In fact, reset-less SDFF cells are slightly smaller and have zero async-reset recovery/removal DRC issues.

GPT Answer

Resetless scannable flops can be initialized through scan and are often fine. Non-scan uninitialized state or uncontrolled capture inputs create X/coverage problems. Functional valid-bit initialization and DFT controllability are separate requirements.

Claude Answer

No. Shift loads every scan flop through SI whether or not it has a reset pin.
Reset-less datapath flops are scan-clean as long as they're on a chain; they only matter for
functional X-propagation, which is a separate proof.

M13Q12 · A11. What is "shadow logic" around a non-scan macro (like an analog PHY interface or a small un-BISTed ROM/RF), and how do wrapper/collar flops recover the lost ATPG fault coverage?

Gemini Answer

• Shadow logic: Combinational gates sitting between the last scan flop and a non-scan macro's input pins (unobservable in ATPG), or between a non-scan macro's output pins and the first downstream scan flop (uncontrollable and X-injecting in ATPG).
• How to recover >99% coverage:
  1. Inputs to black box (Observability): Tap the signals feeding the black box into an XOR tree feeding an observation scan flop (or dedicated collar register).
  2. Outputs from black box (Controllability + X-Bounding): Place a 2:1 scan_mode mux right at the black-box output pins selecting a controllable scan flop (can reuse an existing register!) when scan_mode == 1.

GPT Answer

Collar/shadow logic provides controllable scan inputs to a black-box boundary and observable scan captures of logic driving it. This tests surrounding digital cones; it does not prove the macro interior works. Memories generally need MBIST and analog macros their own tests.

Claude Answer

Logic feeding a black box is unobservable; logic fed by one is uncontrollable and
injects X. Collar: observation flops (or an XOR fold into a scan flop) on the black-box
inputs, and a scan_mode mux that substitutes a scan flop for the black-box outputs.

M13Q13 · A12. Why are multicycle paths (set_multicycle_path) and false paths (set_false_path) critical inputs to the ATPG tool during at-speed transition testing? What happens if an RTL designer forgets to declare a real multicycle path, or declares an overly broad false path?

Gemini Answer

• During at-speed transition ATPG (LOC), the tool pulses 2 clock edges separated by $1\times T_{\text{clk}}$ ($1.56\text{ ns}$).
• Missing a real multicycle path: ATPG generates a pattern that launches a transition on a 2-cycle path and captures it after 1 cycle—the path fails timing on the tester, causing good silicon dies to be thrown in the trash (false test failure / yield loss)!
• Overly broad false path: ATPG masks out real 1-cycle functional paths, letting defective slow silicon escape to customers (DPPM test escape).

GPT Answer

At-speed ATPG needs real clock/path intent so it does not launch/capture impossible or untimed functional transitions. Missing a genuine multicycle restriction can cause invalid one-cycle tests/false failures; broad false paths can suppress genuine fault coverage. Translate exceptions with DFT owners and prove the underlying functional protocol.

Claude Answer

At-speed ATPG launches and captures one period apart. A real 2-cycle path missing
from the ATPG SDC is tested at 1 cycle and fails good silicon; an over-broad false path
masks real defects. Exceptions must be exact and flow to the test SDC.

M13Q14 · A13. During scan shift, thousands of flops toggle simultaneously (50% toggle rate vs. ~5–10% in functional mode). What physical failure can this cause on the tester, and how do DFT/RTL teams mitigate it?

Gemini Answer

• Failure: Shifting random 0/1 patterns toggles ~50% of all chip flip-flops on every clock edge ($5\text{–}10\times$ higher than functional mode), causing huge peak current ($I_{\text{peak}}$) and $L\frac{di}{dt}$ power-grid voltage droop (IR drop) that slows down clock buffers and causes scan-chain hold/setup failures or burns out package bonds.
• Mitigations:
  1. Low-Power ATPG (Adjacent Fill / Repeat Fill): Fill don't-care (X) bits in ATPG vectors with repeating strings (00000... or 11111...) instead of random bits, cutting shift toggles to <10–15%.
  2. Staggered / Phase-Shifted Shift Clocks across physical partitions.
  3. TE = scan_en on ICGs so only active clock-gated islands toggle during capture.

GPT Answer

Excess shift/capture switching causes IR drop, ground bounce, thermal stress and false tester failures or reliability risk. Use lower shift frequency, power-aware ATPG/fill, capture gating, partitioned clocks/chains and power signoff. Slower shifting alone does not cure an overactive at-speed capture.

Claude Answer

Shift toggles ~50% of flops at once: di/dt and IR droop that make good parts fail
timing on the tester. Mitigate with low-power ATPG (repeat-fill), staggered shift across
domains, slower shift clock, TE = scan_en so only enabled domains toggle in capture, and
power-aware pattern limits.

M13Q15 · A14. When you hand-edit a gate-level netlist for a post-freeze ECO and use a SPARE_DFF, why is it better if the spare flop is already stitched into a scan chain (SI tied to D or connected in chain with D tied to Q), and what breaks in ATPG if you re-order the chain?

Gemini Answer

• If a spare SDFF is pre-stitched into the scan chain during initial P&R (.SI connected in chain, .D tied to 1'b0), using that flop in a metal-only ECO only requires re-wiring .D and .Q—the scan chain (SI -> SO) order is 100% unchanged!
• If you splice a new flop into a chain or change the chain order without updating the .spf / .stil scan-chain description file, the ATPG unroller maps bit positions to the wrong physical flip-flops and every scan test fails at bit 1.

GPT Answer

A prestitched compatible scan spare is already controllable/observable and avoids chain surgery. Reordering a chain invalidates tester bit mapping and expected responses unless chain descriptions and patterns are regenerated. SI tied to D alone is not evidence that a flop is actually stitched; verify real connectivity, SE, reset and clock.

Claude Answer

A pre-stitched spare (SI in chain, D tied) lets a metal ECO connect D/Q
without re-ordering the chain. Re-ordering without updating the scan definition (.spf/STIL)
shifts every pattern into the wrong flops, so the whole pattern set is invalid.

Part B — Deep dive: DFT DRC Audit, Fixes and Coverage Recovery (0:20–0:55)

A sub-block of the MAC (clock/reset manager + PHY calibration LUT + SRAM interface) fails
SpyGlass DFT DRC with 6 critical violations and achieves only 84% transition fault
coverage (target: 98.5%). Here is the offending RTL:

module mac_cal_sub (
  input  logic        clk_mac,      // 640 MHz
  input  logic        clk_slow,     // 32 kHz
  input  logic        por_rst_n,    // top-level async reset pin
  input  logic        sw_soft_rst,  // from APB register flop in clk_mac
  input  logic        cal_clk_inv,  // from APB register: invert clock to PHY when 1
  input  logic        clk_gate_en,
  // PHY analog macro interface (black-box in ATPG)
  output logic [15:0] phy_dac_ctrl,
  input  logic [15:0] phy_adc_stat, // unknown (X) during scan!
  // Core datapath
  input  logic [31:0] dp_in,
  output logic [31:0] dp_out
);

  // 1. Internal reset generation
  logic sub_rst_n;
  assign sub_rst_n = por_rst_n & ~sw_soft_rst;

  // 2. Clock inversion & gating
  logic phy_clk, gated_clk;
  assign phy_clk   = cal_clk_inv ? ~clk_mac : clk_mac;
  assign gated_clk = clk_mac & clk_gate_en;

  // 3. Latch-based config staging
  logic [7:0] cfg_lat;
  always_latch begin
    if (clk_slow) cfg_lat = dp_in[7:0];
  end

  // 4. Sequential logic mixing async set and reset from internal logic
  logic [15:0] cal_reg;
  always_ff @(posedge phy_clk or negedge sub_rst_n or posedge sw_soft_rst) begin
    if (!sub_rst_n)        cal_reg <= 16'h0000;
    else if (sw_soft_rst)  cal_reg <= 16'hFFFF;
    else                   cal_reg <= dp_in[15:0];
  end

  // 5. Combinational cloud mixing analog black-box inputs with datapath
  logic [31:0] comb_cone;
  assign comb_cone = (dp_in ^ {cfg_lat, cal_reg, 8'h5A}) + {16'h0, phy_adc_stat};

  always_ff @(posedge gated_clk or negedge sub_rst_n) begin
    if (!sub_rst_n) dp_out <= '0;
    else            dp_out <= comb_cone;
  end

  assign phy_dac_ctrl = dp_in[31:16] & cal_reg;

endmodule

M13Q16 · B1. (15 min) Identify all 6 DFT DRC / ATPG issues

1. (15 min) Identify all 6 DFT DRC / ATPG issues.
   For each numbered region (and the black-box interface): state the exact DFT problem (scan
   controllability, observability, X-propagation, clock/reset DRC), what happens during scan
   shift or capture if left unfixed, and whether it causes a hard DRC failure (blocks scan
   stitching) or a coverage loss.

Gemini Answer

GPT Answer

The supplied 'six' groups actually contain multiple defects. Severity/rule IDs require the real DFT deck, macro models and test architecture; do not invent exact vendor rule names or assume all six are the same kind of failure.

Claude Answer

1. sub_rst_n = por_rst_n & ~sw_soft_rst — async reset driven by an internal flop:
   toggles during shift and wipes chains. Hard DRC failure (uncontrollable async reset).
2. cal_reg async set and reset from the same source — when sw_soft_rst is 1,
   sub_rst_n is 0 too, so set and reset are asserted together (undefined), and the set is
   an internally generated async control. Hard DRC failure.
3. phy_clk = cal_clk_inv ? ~clk_mac : clk_mac and gated_clk = clk_mac & clk_gate_en
   — data-controlled clock polarity and a raw AND gate: uncontrollable/glitchy clocks, and
   the inversion puts flops on the opposite edge during shift. Hard DRC failure.
4. cfg_lat transparent latch — non-scan element, blocks fault propagation, creates
   timing loops in ATPG. DRC failure or large coverage loss.
5. phy_adc_stat into comb_cone — black-box output injects 16 X bits into the adder
   cone and dp_out; in compression it masks the whole slice. Coverage loss.
6. phy_dac_ctrl into a black box — the AND cone is unobservable. Coverage loss.
   Plus: clk_slow has no test-clock path, so its flops have an uncontrollable clock.

M13Q17 · B2. (15 min) Rewrite the RTL to be 100% DFT-clean

2. (15 min) Rewrite the RTL to be 100% DFT-clean.
   Add input logic scan_mode, input logic scan_en (and a standard library icg_cell /
   clk_mux wrapper) and rewrite mac_cal_sub so that:
   • every flop's clock and async reset/set is fully controllable from primary test pins during
     scan_mode,
   • no latch or dual async set/reset hazard blocks scan,
   • phy_adc_stat Xs are bounded (X-bounding) and phy_dac_ctrl outputs are observable so
     comb_cone and the output cone reach >99% fault coverage.

Gemini Answer

module mac_cal_sub (
  input  logic        clk_mac,      // 640 MHz
  input  logic        clk_slow,     // 32 kHz
  input  logic        por_rst_n,    // top-level async reset pin (controllable in ATPG)
  input  logic        sw_soft_rst,  // from APB register flop in clk_mac
  input  logic        cal_clk_inv,  // from APB register: invert clock to PHY when 1
  input  logic        clk_gate_en,
  // DFT pins
  input  logic        scan_mode,    // static 1 during ATPG
  input  logic        scan_en,      // 1 during shift, 0 during capture
  // PHY analog macro interface (black-box in ATPG)
  output logic [15:0] phy_dac_ctrl,
  input  logic [15:0] phy_adc_stat,
  // Core datapath
  input  logic [31:0] dp_in,
  output logic [31:0] dp_out
);

  // FIX 1: Bypass internal reset with top-level por_rst_n during scan_mode
  logic sub_rst_n;
  assign sub_rst_n = scan_mode ? por_rst_n : (por_rst_n & ~sw_soft_rst);

  // FIX 2: Force non-inverted clock during scan_mode & use standard library ICG with .TE(scan_en)
  logic phy_clk, gated_clk;
  logic inv_sel;
  assign inv_sel = cal_clk_inv & ~scan_mode;

  // Library clock inverter mux (forced to positive clk_mac when scan_mode == 1)
  std_clk_xor_mux u_phy_clk_mux (
    .clk_in  (clk_mac),
    .inv_en  (inv_sel),
    .clk_out (phy_clk)
  );

  // Standard library ICG cell: TE connected to scan_en so shift is always clocked
  // and clk_gate_en is tested during capture!
  std_icg_cell u_mac_icg (
    .clk     (clk_mac),
    .en      (clk_gate_en),
    .te      (scan_en),
    .gclk    (gated_clk)
  );

  // FIX 3: Replace transparent latch with an edge-triggered scan-stitchable flip-flop
  logic [7:0] cfg_reg_q;
  always_ff @(posedge clk_slow or negedge sub_rst_n) begin
    if (!sub_rst_n) cfg_reg_q <= '0;
    else            cfg_reg_q <= dp_in[7:0];
  end

  // FIX 4: Make sw_soft_rst a synchronous set so only sub_rst_n is asynchronous
  logic [15:0] cal_reg;
  always_ff @(posedge phy_clk or negedge sub_rst_n) begin
    if (!sub_rst_n)       cal_reg <= 16'h0000;
    else if (sw_soft_rst) cal_reg <= 16'hFFFF;
    else                  cal_reg <= dp_in[15:0];
  end

  // FIX 5: X-bound black-box input phy_adc_stat during scan_mode using existing scan flop cal_reg
  logic [15:0] adc_stat_bounded;
  assign adc_stat_bounded = scan_mode ? cal_reg : phy_adc_stat;

  logic [31:0] comb_cone;
  assign comb_cone = (dp_in ^ {cfg_reg_q, cal_reg, 8'h5A}) + {16'h0, adc_stat_bounded};

  always_ff @(posedge gated_clk or negedge sub_rst_n) begin
    if (!sub_rst_n) dp_out <= '0;
    else            dp_out <= comb_cone;
  end

  assign phy_dac_ctrl = dp_in[31:16] & cal_reg;

  // FIX 6: Observe black-box shadow outputs phy_dac_ctrl via a 1-bit XOR observation scan flop
  logic obs_dac_q;
  always_ff @(posedge gated_clk or negedge sub_rst_n) begin
    if (!sub_rst_n) obs_dac_q <= 1'b0;
    else            obs_dac_q <= ^phy_dac_ctrl;
  end

endmodule

GPT Answer

First agree functional semantics: synchronous soft-clear versus FFFF set; whether cfg needs transparent behavior; safe mode-switch and ADC sampling latency. Replacing a latch with a flop or inserting collar registers can change function/latency and needs approval/equivalence against the corrected specification. The following RTL core illustrates the intended architecture, not a drop-in, proven-100%-clean replacement. Library clock/reset wrappers, CDC mailboxes, scan stitching, OCC and ATPG are required to complete it.

// scan_mode is static throughout test; por_rst_n is a primary test reset.
// func_*_rst_n are per-domain synchronized releases from primary reset.
// soft_clear_* and cfg_update/cfg_word are coherent destination-domain
// commands transferred by acknowledged mailboxes, not raw APB bits.
assign cal_rst_n = scan_mode ? por_rst_n : func_cal_rst_n;
assign dp_rst_n  = scan_mode ? por_rst_n : func_dp_rst_n;
assign cfg_rst_n = scan_mode ? por_rst_n : func_cfg_rst_n;

// Approved clock wrappers, with static configuration while clocks are stopped.
clk_phase_wrapper u_phase (
  .clk_in(clk_mac), .invert_cfg(cal_clk_inv), .clk_out(func_phy_clk)
);
clk_mux u_cal_mux (
  .clk_func(func_phy_clk), .clk_test(test_clk),
  .test_mode(scan_mode), .clk_out(cal_clk)
);
clk_mux u_cfg_mux (
  .clk_func(clk_slow), .clk_test(test_clk),
  .test_mode(scan_mode), .clk_out(cfg_clk)
);
clk_mux u_dp_mux (
  .clk_func(clk_mac), .clk_test(test_clk),
  .test_mode(scan_mode), .clk_out(dp_base_clk)
);
icg_cell u_gate (
  .CK(dp_base_clk), .EN(clk_gate_en),
  .TE(scan_mode && (scan_en || dft_capture_gate_en)), .Q(dp_clk)
);

always_ff @(posedge cfg_clk or negedge cfg_rst_n)
  if (!cfg_rst_n) cfg_q <= '0;
  else if (soft_clear_cfg) cfg_q <= '0;
  else if (cfg_update) cfg_q <= cfg_word;

always_ff @(posedge cal_clk or negedge cal_rst_n)
  if (!cal_rst_n) cal_q <= '0;
  else if (soft_clear_cal) cal_q <= '0;
  else cal_q <= dp_cal_word; // coherent functional transfer contract required

// This collar is scan-inserted. In test capture it holds the value loaded
// during shift; scan insertion must override its functional enable in shift.
always_ff @(posedge dp_clk or negedge dp_rst_n)
  if (!dp_rst_n) adc_collar_q <= '0;
  else if (!scan_mode) adc_collar_q <= phy_adc_stat;

assign adc_for_logic = adc_collar_q;
assign dac_internal = dp_in[31:16] & cal_q;
assign phy_dac_ctrl = scan_mode ? 16'h0000 : dac_internal;

// Scannable observation state sees the cone before analog-output clamp.
always_ff @(posedge dp_clk or negedge dp_rst_n)
  if (!dp_rst_n) dac_observe_q <= '0;
  else dac_observe_q <= dac_internal;

// cfg_dp and cal_dp are coherent dp-domain versions of cfg_q/cal_q.
assign comb_cone = (dp_in ^ {cfg_dp,cal_dp,8'h5A}) + {16'h0,adc_for_logic};
always_ff @(posedge dp_clk or negedge dp_rst_n)
  if (!dp_rst_n) dp_out <= '0;
  else if (soft_clear_dp) dp_out <= '0;
  else dp_out <= comb_cone;

test_clk is the approved OCC output during capture and shift source during shifting. DFT owns its test pin/clock constraints. Functional clk_gate_en must be made safe in test or overridden by the recognized ICG policy. Keep all added collar/control state in the scan model and prevent unknown analog data from being captured during test; the collar permits controlled values, unlike a permanent zero clamp that can hide logic faults. Its functional sampling/CDC behavior needs a real PHY interface contract.

Coverage closure: rerun scan DRC/stitching, test-mode STA, ATPG and fault classification. Analyze the 84% shortfall by uncontrolled clocks/resets, X sources, unobservable cones, excluded macros and untestable faults. Add targeted controls/observations based on evidence. Neither 98.5% nor >99% can be guaranteed from this snippet; denominator, fault model, constraints and macro exclusions matter. Scan proves surrounding digital access; MBIST/analog tests cover their respective interiors.

Claude Answer

module mac_cal_sub (
  input  logic        clk_mac, clk_slow,
  input  logic        por_rst_n,       // top-level async reset pin
  input  logic        sw_soft_rst,     // APB register flop, clk_mac
  input  logic        cal_clk_inv, clk_gate_en,
  input  logic        scan_mode, scan_en,
  output logic [15:0] phy_dac_ctrl,
  input  logic [15:0] phy_adc_stat,
  input  logic [31:0] dp_in,
  output logic [31:0] dp_out
);
  // 1/2. One async reset: the pin. Soft reset becomes a synchronous clear/set.
  logic sub_rst_n, soft_rst;
  assign sub_rst_n = por_rst_n;
  assign soft_rst  = sw_soft_rst;                   // synchronous; plain data in capture

  // 3. Clocks: library cells only, polarity bypassed in scan_mode, ICG with TE = scan_en.
  logic phy_clk, gated_clk, inv_sel, clk_slow_t;
  assign inv_sel = cal_clk_inv & ~scan_mode;
  clk_mux2 u_phy_clk  (.clk0(clk_mac), .clk1(~clk_mac), .sel(inv_sel), .clk_o(phy_clk));
  icg_cell u_gate     (.CK(clk_mac), .EN(clk_gate_en), .TE(scan_en), .ECK(gated_clk));
  clk_mux2 u_slow_mux (.clk0(clk_slow), .clk1(clk_mac), .sel(scan_mode), .clk_o(clk_slow_t));

  // 4. Latch -> flop on a scan-controllable clock.
  logic [7:0] cfg_q;
  always_ff @(posedge clk_slow_t or negedge sub_rst_n)
    if (!sub_rst_n) cfg_q <= '0;
    else            cfg_q <= dp_in[7:0];

  // 2. cal_reg: async reset from the pin only, soft reset as synchronous set.
  logic [15:0] cal_reg;
  always_ff @(posedge phy_clk or negedge sub_rst_n)
    if (!sub_rst_n)    cal_reg <= 16'h0000;
    else if (soft_rst) cal_reg <= 16'hFFFF;
    else               cal_reg <= dp_in[15:0];

  // 5. X-bounding: in scan_mode substitute an existing scan flop for the analog input.
  logic [15:0] adc_bounded;
  assign adc_bounded = scan_mode ? cal_reg : phy_adc_stat;

  logic [31:0] comb_cone;
  assign comb_cone = (dp_in ^ {cfg_q, cal_reg, 8'h5A}) + {16'h0, adc_bounded};

  always_ff @(posedge gated_clk or negedge sub_rst_n)
    if (!sub_rst_n)    dp_out <= '0;
    else if (soft_rst) dp_out <= '0;
    else               dp_out <= comb_cone;

  // 6. Observability: fold the black-box input into observation scan flops.
  assign phy_dac_ctrl = dp_in[31:16] & cal_reg;
  logic [3:0] dac_obs_q;
  always_ff @(posedge clk_mac or negedge sub_rst_n)
    if (!sub_rst_n) dac_obs_q <= '0;
    else            dac_obs_q <= {^phy_dac_ctrl[15:12], ^phy_dac_ctrl[11:8],
                                  ^phy_dac_ctrl[7:4],   ^phy_dac_ctrl[3:0]};
endmodule

Notes: clk_mux2 is the library glitch-free mux; if the design needs the soft reset to be
asynchronous functionally, keep it async but mux it with scan_mode (scan_mode ? por_rst_n : por_rst_n & ~sw_soft_rst_sync) through a reset synchronizer. The four observe
flops see every single stuck-at on the 16 AND outputs; use the full 16 if aliasing matters.

M13Q18 · B3. (5 min) At-Speed SDC Exceptions

3. (5 min) At-Speed SDC Exceptions.
   In functional mode, clk_slow (32 kHz) and clk_mac (640 MHz) never interact at 640 MHz.
   During ATPG capture, if both domains are pulsed by the scan clock / OCC, what happens on
   paths between clk_slow flops and clk_mac flops, and how does the DFT SDC handle inter-clock
   capture?

Gemini Answer

Task 3: At-Speed ATPG Capture Across clk_slow (cfg_reg_q) and clk_mac (dp_out)

• Problem: During scan shift, both clk_slow and clk_mac are driven by the slow tester scan_clk (with a lockup latch between the clk_slow chain segment and clk_mac chain segment). During at-speed capture, if both OCCs fire simultaneously, ATPG will attempt a 640 MHz ($1.56\text{ ns}$) transition check from cfg_reg_q (clk_slow) through comb_cone to dp_out (clk_mac), which is an asynchronous/quasi-static crossing in functional mode!
• Fix in ATPG / DFT Setup:
  1. One-Hot Clock Grouping in ATPG: OCCs are configured so only one clock domain (clk_mac OR clk_slow) pulses at-speed per pattern, while the other domain's clock stays gated low during capture (cfg_reg_q holds its shifted-in value steady as a pseudo-primary input!).
  2. ATPG SDC: Declare set_clock_groups -asynchronous -group {clk_mac} -group {clk_slow} (or set_false_path -from [get_clocks clk_slow] -to [get_clocks clk_mac]) in the ATPG timing exceptions file.

GPT Answer

Pulsing formerly unrelated slow/fast domains with one OCC source can create a test-only one-cycle launch/capture relationship that functional hardware never requires. ATPG must use the approved domain capture schedule and valid path exceptions; mask/disable illegal inter-domain launches or use staggered/per-domain capture where appropriate. Do not blindly make all crossings 640 MHz synchronous or broadly false-path every cross-domain cone. Review both functional CDC safety and test-mode controllability/hold, and report fault coverage excluded by the chosen schedule.

Claude Answer

In capture, if both domains are pulsed, ATPG will launch from cfg_q and capture in
dp_out one at-speed period later and fail good silicon on a path with no functional
timing requirement. In the test SDC declare them asynchronous
(set_clock_groups -asynchronous or set_false_path both ways between clk_slow_t and
clk_mac_t) and have ATPG mask inter-clock capture (one domain per capture procedure, or
multi-clock capture with the cross paths masked). With clk_slow_t muxed to clk_mac in
scan mode, the path is physically the same clock, so the OCC capture procedure must still
treat it as a multicycle/false path — the SDC exception is what keeps that honest.

Part C — Your questions (0:55–1:00)

M13Q19 · C1. Questions for the interviewer

Gemini Answer

1. "Do RTL engineers here run SpyGlass DFT DRC locally before opening a merge request, and are zero DFT warnings required at RTL freeze?"
2. "How are multi-clock at-speed capture patterns structured on your chips—do you pulse one OCC domain at a time or run simultaneous multi-domain capture?"
3. "What is your strategy for wrapper/collar insertion around analog PHY interfaces and small custom macros?"

GPT Answer

Which RTL DFT checks gate release? How are shift/capture clock enables specified? Who owns collar insertion, analog X models, and fault-exclusion review?

Claude Answer

1. Is DFT DRC in the RTL designer's CI loop, and what are the stuck-at and transition
   targets for the MAC?
2. Are chains stitched at block or top level, and who owns the test SDC exceptions?
3. How much coverage is lost today to black boxes and X sources, and is collar insertion
   automated?

Additional notes

Notes. Material not tied to a question

Gemini Answer

No answer in gemini_answer.md.

GPT Answer

Reference

Siemens: Navigating Tessent OCCs gives vendor context for OCC-based test clock control. Actual capture schedules, DRC rules and coverage claims require the project's test setup and reports.

Claude Answer

No answer in claude_answer.md.