RTL Review

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Round 11 — Combined answers (Gemini · GPT · Claude)

Contents

0. Resume probe

M11Q1 · "Walk me through the host/SoC and baseband interfaces of your Wi-Fi MAC: which standard protocols did they use, and where did you have to bridge between streaming and memory-mapped semantics?"

Gemini Answer

GPT Answer

"I own the MAC baseband interface and RTL releases to SoC integration, and built a MAC-to-MAC emulation bridge. My resume does not name the host bus, descriptor format or AXI implementation I used, so I would distinguish my actual integration experience from the proposed AXI design below."

Claude Answer

Template (replace with the real protocols):

"Three boundaries. Host/SoC: an AXI4 DMA master for descriptors and payload and an
APB/AXI4-Lite slave for CSRs and interrupts; that is where memory-mapped semantics live.
MAC-to-baseband: packet-oriented streaming, valid/ready byte streams with TXVECTOR/RXVECTOR
as sideband, plus a handful of timing-critical strobes (tx_start, rx_end, CCA) that are
not transactions at all but µs-accurate events. The bridging happens twice: Tx DMA turns
bursty memory reads into a continuous stream the PHY can't stall, so it needs a prefetch
FIFO sized for memory latency; Rx DMA turns a stream that can't be stalled into memory
writes with 4 KB-split bursts and descriptor completions. The baseband side taught me to
treat latency budgets as protocol: SIFS is the constraint, not AXI."

Part A — Rapid-fire Q and A (0:05–0:20)

M11Q2 · A1. Name the five AXI4 channels and state the fundamental valid/ready handshake rule regarding combinational dependencies between xVALID and xREADY.

Gemini Answer

GPT Answer

AW address, W write data, B write response, AR read address, R read data. Transfer occurs on VALID && READY. A sender must not wait for READY before asserting VALID and must hold VALID/payload until acceptance. AXI also prohibits combinational input-to-output paths at an interface; READY may be conditionally generated through registered logic without imposing a sender dependency.

Claude Answer

AW, W, B, AR, R. A source must not wait for READY to assert VALID; once VALID
is asserted, it and the payload hold until the handshake. A sink may wait for VALID
before READY. So READY may depend combinationally on VALID, never the reverse.

Gemini Answer

GPT Answer

A slave can wait for both AWVALID and WVALID before raising AWREADY; the manager cannot wait for AWREADY to offer WVALID. BVALID requires accepted AW and accepted final W beat, not merely seeing WLAST asserted, and cannot depend on BREADY.

Claude Answer

Yes, a slave may wait for both AWVALID and WVALID before asserting either
READY, which is exactly why a master must not hold WVALID back until AWREADY. And yes,
BVALID must wait for the WLAST handshake (and the AW handshake) to complete.

M11Q4 · A3. Why does AXI forbid a burst from crossing a 4 KB address boundary? What hardware savings does this give the interconnect and slaves?

Gemini Answer

GPT Answer

A 4 KB boundary is a decoding/protection granule: keeping a burst inside it avoids splitting one transaction across independently decoded destinations and simplifies routing/response handling. Do not infer the physical memory page size from this protocol rule.

Claude Answer

4 KB is the minimum page and the usual decode granularity, so a burst that stays
inside a page targets exactly one slave and one translation. Interconnects and slaves then
only increment addr[11:0] with a 12-bit adder, with no re-decode mid-burst.

M11Q5 · A4. AWLEN, AWSIZE, AWBURST: what do they encode, what is the maximum burst length in AXI4 for INCR vs. WRAP, and how many bytes are transferred in one beat when AWSIZE = 3'b010 on a 64-bit bus?

Gemini Answer

GPT Answer

AWLEN is beats minus one; AWSIZE is log2(bytes per beat); AWBURST selects FIXED/INCR/WRAP. AXI4 INCR permits 1-256 beats, WRAP 2/4/8/16 with alignment rules. AWSIZE=2 means up to four valid byte lanes per beat even on a 64-bit bus.

Claude Answer

AWLEN = beats − 1: INCR 1–256, WRAP 2/4/8/16, FIXED 1–16. AWSIZE = log2(bytes per
beat): 3'b010 = 4 bytes per beat on a 64-bit bus (a narrow transfer). AWBURST =
FIXED/INCR/WRAP.

M11Q6 · A5. Narrow transfers and byte lanes: on a 64-bit AXI bus (WSTRB[7:0]), a master issues a 32-bit INCR burst (AWSIZE = 3'b010) starting at address 0x1004. Which WSTRB bits are active on beat 0 and beat 1?

Gemini Answer

GPT Answer

For full 32-bit transfers: at 0x1004 use WSTRB=8'hF0; at 0x1008 use 8'h0F. Data bytes must occupy those lanes too.

Claude Answer

0x1004 → addr[2:0] = 4, upper half of the 64-bit lane: beat 0 WSTRB = 8'b1111_0000;
beat 1 at 0x1008 → addr[2:0] = 0: WSTRB = 8'b0000_1111.

M11Q7 · A6. AXI IDs (AWID/BID, ARID/RID): what are the ordering rules for transactions with the same ID versus different IDs? Why did AXI4 remove WID (which existed in AXI3)?

Gemini Answer

GPT Answer

Same-ID responses preserve the protocol's ordering within their read/write stream; different IDs allow reordering, and R beats of different IDs may interleave. Equal numeric read/write IDs do not create a general cross-direction ordering barrier. AXI4 removed write-data interleaving/WID: W bursts follow address issue order, without interleaving different transactions.

Claude Answer

Same ID: responses (and write data) strictly in issue order. Different IDs: may
complete out of order. WID was removed because AXI3 write-data interleaving forced slaves
to buffer and re-sort W beats for little gain; AXI4 requires W beats in AW order.

M11Q8 · A7. Give a concrete scenario where two masters and two slaves connected through an AXI crossbar deadlock, even though every module obeys individual channel handshake rules.

Gemini Answer

GPT Answer

Example: M0 issues writes S0 then S1; M1 issues S1 then S0. A poorly designed crossbar lets S0's service head wait for M1's second W burst and S1's head wait for M0's second, while each manager must send its first W burst first and there is no buffering to bypass either head. Channel-local handshake compliance does not remove that cyclic resource wait. Preserve consistent AW/W routing order or buffer/reserve complete transactions to break it.

Claude Answer

Master 0 issues AW to slave A then slave B; master 1 issues AW to B then A. Each
slave waits for the W data of the AW it accepted first; each master sends W in its own AW
order; the crossbar's shared W path to A is held by master 1's pending data and to B by
master 0's → circular wait, every handshake legal. Also: a master whose RREADY depends on
getting BVALID, talking through a slave that serialises writes behind reads.

M11Q9 · A8. APB (PSEL, PENABLE, PREADY, PWRITE, PSLVERR): draw/speak the minimum cycle count for a write with zero wait states vs. two wait states. Why use APB for CSRs instead of AXI4-Lite?

Gemini Answer

GPT Answer

APB has one setup cycle (PSEL=1,PENABLE=0) and one or more access cycles (PENABLE=1). Zero wait: two cycles; two wait states: four. Sample response/error at completion. APB suits simple low-bandwidth CSRs with a small slave interface; AXI-Lite offers independent address/data channels and more concurrency at greater control complexity.

Claude Answer

Zero wait states: 2 cycles (setup: PSEL=1, PENABLE=0; access: PENABLE=1, PREADY=1). Two wait states: 4 cycles (PENABLE held until PREADY). APB for CSRs because
one unpipelined shared bus costs a few hundred gates and a handful of wires per slave,
which is what you want for hundreds of slow registers.

M11Q10 · A9. Your Wi-Fi MAC block has a soft-reset register bit written by firmware over APB while its AXI DMA master has 4 read bursts in flight on the SoC fabric. What happens if you just reset the DMA FSM immediately, and what is the right hardware sequence?

Gemini Answer

GPT Answer

Immediate DMA reset forgets outstanding R responses and can hang the fabric or misassociate stale data after restart. Block new work, drain all accepted transactions, preserve response acceptance/IDs, then reset local state and advance an epoch. A timeout needs a fabric-supported abort/isolation mechanism, not silently dropping traffic.

Claude Answer

Resetting the FSM immediately drops RREADY/BREADY and abandons outstanding
AR/AW bursts, so the fabric waits forever (or until a timeout) and other masters hang
behind it. Right sequence: stop issuing new addresses; keep RREADY=1, BREADY=1; finish
any W burst already started (dummy beats with WSTRB=0 to WLAST if the source is gone);
wait for outstanding == 0; then ack the soft reset and clear internal state.

M11Q11 · A10. What is the difference between DECERR and SLVERR in AXI BRESP/RRESP? Who generates each, and can a slave return EXOKAY on a normal non-exclusive access?

Gemini Answer

GPT Answer

DECERR usually means interconnect/default-slave decode failure; SLVERR means the addressed subordinate could not complete the operation successfully. EXOKAY is reserved for successful exclusive access, not normal transactions.

Claude Answer

SLVERR from the target slave (illegal register, overflow, parity). DECERR from
the interconnect decoder when no slave claims the address. EXOKAY only for exclusive
accesses; a normal access gets OKAY.

M11Q12 · A11. How do AWCACHE / ARCACHE (bufferable, modifiable, allocate) and early write response (BVALID before data reaches the final destination) affect firmware that writes a DMA descriptor to DRAM and immediately rings a hardware doorbell register?

Gemini Answer

GPT Answer

Early completion and memory attributes do not replace software coherency/ordering. Publish descriptor data, clean caches if noncoherent, apply required release/barrier operations, then ring the MMIO doorbell. Hardware must use the agreed coherent/ordered path and avoid stale descriptor prefetch. Attributes must match the system memory model.

Claude Answer

With bufferable writes the fabric may return BVALID from an intermediate buffer
before the descriptor is visible at the coherence point; firmware then rings the doorbell
over a faster path and the DMA reads a stale descriptor. Fix: non-bufferable descriptor
writes or a barrier (DSB) that waits for the write response from the serialisation
point before the MMIO doorbell; hardware side, read the descriptor through the same
coherent path.

M11Q13 · A12. You need to sustain 25.6 Gbps of payload throughput over a 64-bit AXI4 interface running at 640 MHz, where the memory subsystem has a 40-cycle read latency. What is the minimum number of outstanding read beats (and bursts) your master must support to avoid bubbles?

Gemini Answer

GPT Answer

Payload demand is 25.6e9/(64*640e6)=0.625 beat/cycle. Latency-bandwidth product is at least ceil(40*0.625)=25 beats in flight, before overhead/margin. With 16-beat bursts, at least two bursts by this simplified bound. Sustaining the full one-beat/cycle bus would require at least 40 beats, or three such bursts, plus practical margin. Burst count is not uniquely defined without burst length.

Claude Answer

25.6 Gb/s = 3.2 GB/s. The bus peaks at 8 B × 640 MHz = 5.12 GB/s, so 62.5%
utilisation. Little's law: 40 cycles × 0.625 beats/cycle = 25 beats in flight, so at least
two 16-beat bursts (32 beats) outstanding, three in practice for jitter.

M11Q14 · A13. What is an AXI register slice, how does it differ from a simple flop stage on the bus, and why do physical design teams ask for full vs. forward-only vs. backward-only slices?

Gemini Answer

GPT Answer

A register slice is an elastic protocol stage preserving stability/conservation on each affected channel. A plain flop can overwrite stalled data. Forward slices cut valid/data, backward slices cut ready and need spill capacity; full slices cut both. PD selects them to break long timing paths while architecture budgets latency/storage.

Claude Answer

A register slice is a 2-entry skid buffer that cuts both the forward
VALID/payload path and the backward READY path with zero throughput loss. A plain flop
stage halves throughput or breaks the handshake. Forward-only registers only VALID/payload
(READY stays combinational); backward-only registers only READY. PD asks per net
depending on which direction crosses the long distance.

M11Q15 · A14. Compare a shared-bus crossbar against a packetized Network-on-Chip (NoC): when does a crossbar stop scaling in physical implementation?

Gemini Answer

GPT Answer

Crossbars grow muxing, centralized wires and arbitration roughly with endpoint connectivity. A NoC distributes routing and pipelines long wires at the cost of packet overhead, buffering, routing/virtual-channel complexity and latency. Floorplan distance and traffic locality, not a fixed endpoint count, determine crossover.

Claude Answer

Crossbar cost grows as masters × slaves in wires and mux fan-in; around 8×8, or
when the endpoints are millimetres apart, routing congestion and the mux timing push you
to a packetised NoC with routers, links and credit flow control.

M11Q16 · A15. In your UCLA Neural Network Accelerator or MAC datapath, how do you bridge a continuous streaming interface (AXI-Stream / valid-ready) into bursty memory-mapped AXI4 writes?

Gemini Answer

GPT Answer

Buffer stream data/byte qualifiers and packet metadata, assemble bounded bursts, split boundaries, generate ordered AW/W, track B responses, then publish completion. Handle partial tails, capacity overflow and source stalls. My resume does not establish that my UCLA accelerator used AXI.

Claude Answer

Buffer the stream in a packet/burst FIFO; track occupancy and EOF; only issue an
AW when the whole burst is already in the FIFO, so a stalled stream can never hold the
shared W channel; keep enough outstanding bursts to cover memory latency.

Part B — Deep dive: Streaming-to-AXI4 DMA Write Engine with 4 KB Splitter (0:20–0:55)

You are designing the Rx packet capture / frame-dump DMA engine for a MAC/baseband test and
production path. Incoming frames arrive over a 64-bit streaming interface:

// Stream input (same 640 MHz clk)
input  logic        s_valid,
output logic        s_ready,
input  logic [63:0] s_data,
input  logic [7:0]  s_keep,   // byte qualifier, contiguous from LSB on last beat
input  logic        s_last,

// Descriptor interface (from FW ring)
input  logic        desc_valid,
output logic        desc_ready,
input  logic [39:0] desc_base_addr, // 8-byte aligned start address
input  logic [15:0] desc_max_bytes, // buffer capacity
output logic        cpl_valid,
input  logic        cpl_ready,
output logic [15:0] cpl_bytes_written,
output logic        cpl_status_err  // set on AXI error or buffer overflow

The engine writes each packet into system memory over a 64-bit AXI4 Master (AW, W, B
channels, MAX_BURST_LEN = 16 beats, up to 8 outstanding write transactions, AWID = 0).

M11Q17 · B1. (10 min) Microarchitecture and 4 KB Boundary Splitter

(10 min) Microarchitecture & 4 KB Boundary Splitter.
Draw the block diagram: payload FIFO, descriptor tracker, address/burst-length generator,
and B-channel completion tracker. Specifically explain:

Gemini Answer

               +-------------------------------------------------------+
  s_valid ---->| Payload FIFO (64b data + 8b keep + 1b last, depth 64) |
  s_data  ---->|   tracks: fifo_occ_beats, eof_in_fifo_cnt             |
  s_last  ---->+-------------------------------------------------------+
                                  | (pop on WVALID && WREADY)
                                  v
  desc_valid ->+-------------------------------------------------------+
  base_addr  ->| Burst Splitter & AW/W Channel Coordinator             |--> m_axi_aw*
  max_bytes  ->|   curr_addr_q[39:0], rem_buf_beats_q                  |--> m_axi_w*
               |   next_burst_beats = min(16, beats_to_4k, avail_beats)|
               +-------------------------------------------------------+
                                  | (on packet last AW issued: push exp_b_cnt)
                                  v
               +-------------------------------------------------------+
  m_axi_b* --->| B-Channel Completion Tracker Queue                    |--> cpl_valid
               |   waits until all bursts of packet receive BVALID     |--> cpl_bytes
               +-------------------------------------------------------+

GPT Answer

descriptor latch -> capacity/packet tracker; stream -> payload FIFO(data,keep,last) -> W engine; burst builder -> AW holding register; AW/B counters -> completion/error accumulator.

For an 8-byte-aligned address:

beats_to_4k = 10'd512 - {1'b0, curr_addr[11:3]}; // 1..512
n = min(remaining_beats, beats_to_4k, 16);
AWLEN = 8'(n - 1); // only when n > 0

Use at least ten bits for 512; a 12-bit literal cannot represent 4096. Restrict n to remaining descriptor capacity and the current packet. Capacity counts valid bytes, not just full beats; clip the final WSTRB so no byte outside the descriptor is written. Address arithmetic is 40 bits with explicit overflow/error handling.

Choose store-and-forward per burst: offer AW and its W data once all selected beats are buffered, or EOF gives a short tail. It avoids occupying the fabric waiting for future source data. The FIFO must have space for at least one maximum burst; provision more for throughput/credit latency. Do not wait for the entire packet, since it can exceed FIFO capacity.

Claude Answer

Blocks: payload FIFO (packet-aware: counts beats of the current packet and whether its
EOF is present), descriptor tracker (curr_addr, remaining_beats, bytes_written),
burst generator (below), W engine fed by a small burst queue (beats per committed burst,
in AW order), B tracker (per-burst "last of packet" flag FIFO + sticky error), completion
interface.

4 KB math with 8-byte beats (512 beats per page): beats to the boundary are
512 − addr[11:3]; since bursts are ≤ 16, only the last 128 bytes matter:

max_4k      = (curr_addr[11:7] == 5'h1F) ? (5'd16 - {1'b0, curr_addr[6:3]}) : 5'd16;
burst_beats = min(max_4k, min(avail_beats, remaining_beats), 16);
awlen       = burst_beats - 1;

Store-and-forward per burst: issue AW only when the FIFO already holds the whole burst
(or the packet's EOF). Otherwise a radio stall mid-packet parks our W channel with a burst
half-sent, and the fabric serialises every other master behind it — the deadlock the
architect has debugged. Utilisation is unaffected: with 8 outstanding bursts the FIFO only
needs to run one burst ahead of the W engine.

M11Q18 · B2. (15 min) Live Coding — Burst Splitter and AW/W Channel Coordinator

(15 min) Live Coding — Burst Splitter & AW/W Channel Coordinator.
Write the synthesizable SystemVerilog for the AW burst calculation and handshake FSM
that takes (curr_addr, avail_beats, pkt_eof_seen) and drives m_axi_awvalid,
m_axi_awaddr, m_axi_awlen while keeping AW and W ordered.

Gemini Answer

module dma_axi_burst_ctrl (
  input  logic        clk,
  input  logic        rst_n,

  // Soft reset quiescence handshake
  input  logic        soft_rst_req,
  output logic        soft_rst_ack,

  // From Descriptor Loader
  input  logic        pkt_active,
  input  logic [39:0] pkt_start_addr, // 8B aligned
  input  logic        pkt_start_load,

  // From Stream Payload FIFO
  input  logic [6:0]  fifo_occ_beats, // beats currently in FIFO up to first EOF
  input  logic        fifo_has_eof,   // true if s_last for current packet is in FIFO
  output logic        fifo_pop,
  input  logic [63:0] fifo_rdata,
  input  logic [7:0]  fifo_rkeep,
  input  logic        fifo_rlast,

  // AXI4 Write Master (AW, W, B)
  output logic        m_axi_awvalid,
  input  logic        m_axi_awready,
  output logic [39:0] m_axi_awaddr,
  output logic [7:0]  m_axi_awlen,
  output logic [2:0]  m_axi_awsize,
  output logic [1:0]  m_axi_awburst,

  output logic        m_axi_wvalid,
  input  logic        m_axi_wready,
  output logic [63:0] m_axi_wdata,
  output logic [7:0]  m_axi_wstrb,
  output logic        m_axi_wlast,

  input  logic        m_axi_bvalid,
  output logic        m_axi_bready,
  input  logic [1:0]  m_axi_bresp
);

  assign m_axi_awsize  = 3'b011; // 8 bytes per beat
  assign m_axi_awburst = 2'b01;  // INCR
  assign m_axi_bready  = 1'b1;   // Always ready to accept write responses

  logic [39:0] curr_addr_q;
  logic [4:0]  w_beats_rem_q;    // Remaining W beats to send for active burst
  logic [3:0]  outst_b_cnt_q;    // Outstanding bursts waiting for BVALID
  logic        aw_pending_q;     // AWVALID held until AWREADY

  // 1-cycle 4KB boundary limit (capped at 16 beats)
  logic [4:0] max_beats_4k;
  logic [4:0] avail_capped;
  logic [4:0] next_burst_beats;
  logic       can_launch_burst;

  assign max_beats_4k     = (curr_addr_q[11:7] == 5'b11111)
                          ? (5'd16 - {1'b0, curr_addr_q[6:3]})
                          : 5'd16;
  assign avail_capped     = (fifo_occ_beats > 7'd16) ? 5'd16 : fifo_occ_beats[4:0];
  assign next_burst_beats = (avail_capped < max_beats_4k) ? avail_capped : max_beats_4k;

  // Launch a burst when no burst is currently streaming W beats, <8 outstanding B's,
  // not in soft reset, and either FIFO has enough beats to fill max_beats_4k OR EOF is in FIFO.
  assign can_launch_burst = pkt_active && !soft_rst_req &&
                            (w_beats_rem_q == 5'd0) && !aw_pending_q &&
                            (outst_b_cnt_q < 4'd8) && (fifo_occ_beats != 7'd0) &&
                            ((fifo_occ_beats >= {2'b0, max_beats_4k}) || fifo_has_eof);

  wire aw_fire = m_axi_awvalid && m_axi_awready;
  wire w_fire  = m_axi_wvalid  && m_axi_wready;
  wire b_fire  = m_axi_bvalid  && m_axi_bready;

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      curr_addr_q   <= '0;
      m_axi_awlen   <= '0;
      aw_pending_q  <= 1'b0;
      w_beats_rem_q <= '0;
      outst_b_cnt_q <= '0;
    end else begin
      // Address initialization or post-burst advance
      if (pkt_start_load) begin
        curr_addr_q <= pkt_start_addr;
      end else if (can_launch_burst) begin
        m_axi_awlen   <= {3'b0, next_burst_beats - 5'd1};
        aw_pending_q  <= 1'b1;
        w_beats_rem_q <= next_burst_beats;
      end else begin
        if (aw_fire) begin
          aw_pending_q <= 1'b0;
          curr_addr_q  <= curr_addr_q + ({32'b0, m_axi_awlen + 8'd1} << 3);
        end
        if (w_fire) begin
          w_beats_rem_q <= w_beats_rem_q - 5'd1;
        end
      end

      // Track outstanding bursts for B-channel completion and soft-reset quiescence
      outst_b_cnt_q <= outst_b_cnt_q + (can_launch_burst ? 4'd1 : 4'd0)
                                     - (b_fire           ? 4'd1 : 4'd0);
    end
  end

  assign m_axi_awvalid = aw_pending_q;
  assign m_axi_awaddr  = curr_addr_q;

  assign m_axi_wvalid  = (w_beats_rem_q != 5'd0);
  assign m_axi_wdata   = fifo_rdata;
  assign m_axi_wstrb   = fifo_rkeep;
  assign m_axi_wlast   = (w_beats_rem_q == 5'd1);
  assign fifo_pop      = w_fire;

  // Quiescent when no AW, no W beats remaining, and 0 outstanding B responses
  assign soft_rst_ack  = soft_rst_req && !aw_pending_q &&
                         (w_beats_rem_q == 5'd0) && (outst_b_cnt_q == 4'd0);

endmodule

GPT Answer

This synthesizable control core assumes an upstream packet FIFO with a stable head, avail_beats counting complete unreserved beats, and descriptor capacity already enforced. It is not a complete descriptor/overflow/completion engine. It holds AW stable, presents W independently of AWREADY, sends one burst's W at a time, and allows up to eight accepted AW transactions awaiting B. It inserts a launch bubble between bursts; remove that with queued burst descriptors if peak throughput requires it. AXI clock/reset and full sideband wiring follow the integration contract.

// Inside a module; signals with _q are registers.
logic active_q, aw_pending_q, sticky_err_q;
logic [39:0] addr_q, awaddr_q;
logic [4:0] left_q;
logic [7:0] awlen_q;
logic [3:0] outstanding_q;
logic [9:0] boundary_beats, take;
logic aw_fire, w_fire, b_fire, aw_done, w_done;

always_comb begin
  boundary_beats = 10'd512 - {1'b0,addr_q[11:3]};
  take = (avail_beats < boundary_beats) ? avail_beats : boundary_beats;
  if (take > 10'd16) take = 10'd16;
end
assign m_axi_awvalid = active_q && aw_pending_q;
assign m_axi_awaddr = awaddr_q;
assign m_axi_awlen = awlen_q;
assign m_axi_awsize = 3'd3;
assign m_axi_awburst = 2'b01;
assign m_axi_awid = '0;
assign m_axi_wvalid = active_q && (left_q != 0) && fifo_valid;
assign m_axi_wdata = fifo_data;
assign m_axi_wstrb = fifo_keep;
assign m_axi_wlast = (left_q == 5'd1);
assign fifo_pop = m_axi_wvalid && m_axi_wready;
assign m_axi_bready = 1'b1; // completion/error storage is reserved
assign aw_fire = m_axi_awvalid && m_axi_awready;
assign w_fire = m_axi_wvalid && m_axi_wready;
assign b_fire = m_axi_bvalid && m_axi_bready;
assign aw_done = !aw_pending_q || aw_fire;
assign w_done = (left_q == 0) || (w_fire && left_q == 5'd1);

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    active_q <= 1'b0;
    aw_pending_q <= 1'b0;
    addr_q <= '0;
    awaddr_q <= '0;
    awlen_q <= '0;
    left_q <= '0;
    outstanding_q <= '0;
    sticky_err_q <= 1'b0;
  end else begin
    // desc_load is allowed only when idle and all prior B responses retired.
    if (desc_load) begin
      addr_q <= desc_base_addr;
      sticky_err_q <= 1'b0;
    end
    if (!active_q && !desc_load && packet_active && !soft_rst_req &&
        (outstanding_q < 4'd8) && (take != 0) &&
        ((take == 10'd16) || pkt_eof_seen ||
         (take == boundary_beats))) begin
      active_q <= 1'b1;
      aw_pending_q <= 1'b1;
      awaddr_q <= addr_q;
      awlen_q <= 8'(take - 10'd1);
      left_q <= 5'(take);
      addr_q <= addr_q + (40'(take) << 3);
    end
    if (aw_fire) aw_pending_q <= 1'b0;
    if (w_fire) left_q <= left_q - 5'd1;
    if (active_q && aw_done && w_done) active_q <= 1'b0;
    case ({aw_fire,b_fire})
      2'b10: outstanding_q <= outstanding_q + 4'd1;
      2'b01: outstanding_q <= outstanding_q - 4'd1;
      default: ;
    endcase
    if (b_fire && m_axi_bresp != 2'b00) sticky_err_q <= 1'b1;
  end
end

All selected FIFO beats are reserved for this burst; no second consumer may remove them. The producer must never combine different packets within avail_beats. Add protocol assertions for unexpected B, outstanding count bounds, AW/W payload stability, WLAST position and 4 KB confinement. Clearing a packet must not clear protocol state while traffic is outstanding. Code compilation/simulation is unverified here.

Claude Answer

module aw_burst_gen #(parameter int MAX_OUT = 8) (
  input  logic        clk, rst_n,
  // descriptor / packet tracker
  input  logic        seg_active,       // descriptor loaded, packet in progress
  input  logic [39:0] curr_addr,        // 8-byte aligned next write address
  input  logic [15:0] remaining_beats,  // buffer capacity left, in beats
  // payload FIFO (current packet only, excluding beats already reserved)
  input  logic [5:0]  avail_beats,
  input  logic        pkt_eof_seen,     // EOF of the current packet is in the FIFO
  // AXI AW
  output logic        m_axi_awvalid,
  input  logic        m_axi_awready,
  output logic [39:0] m_axi_awaddr,
  output logic [7:0]  m_axi_awlen,
  output logic [2:0]  m_axi_awsize,
  output logic [1:0]  m_axi_awburst,
  // W burst queue (to the W engine), same order as AW
  output logic        wq_push,
  output logic [4:0]  wq_beats,
  input  logic        wq_full,
  // outstanding = AW accepted - B received
  input  logic [3:0]  outstanding,
  // back to the tracker
  output logic        burst_commit,
  output logic [4:0]  burst_beats_o,
  output logic [39:0] next_addr
);
  logic [4:0] max_4k, max_fifo, max_rem, target, burst_beats;
  logic       enough, can_issue;

  assign max_4k   = (curr_addr[11:7] == 5'h1F) ? (5'd16 - {1'b0, curr_addr[6:3]}) : 5'd16;
  assign max_rem  = (remaining_beats > 16'd16) ? 5'd16 : remaining_beats[4:0];
  assign max_fifo = (avail_beats     > 6'd16)  ? 5'd16 : avail_beats[4:0];
  assign target   = (max_rem < max_4k) ? max_rem : max_4k;        // what we'd like to send
  // store-and-forward: the whole burst (or the packet tail) must be in the FIFO
  assign enough      = pkt_eof_seen | (max_fifo >= target);
  assign burst_beats = (max_fifo < target) ? max_fifo : target;   // only smaller at EOF

  assign can_issue = seg_active & enough & (burst_beats != 5'd0)
                   & (outstanding < 4'(MAX_OUT)) & ~wq_full
                   & (~m_axi_awvalid | m_axi_awready);             // AW register free

  assign burst_commit  = can_issue;
  assign burst_beats_o = burst_beats;
  assign next_addr     = curr_addr + {35'd0, burst_beats, 3'b000};
  assign wq_push       = can_issue;                                // W starts independently
  assign wq_beats      = burst_beats;

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      m_axi_awvalid <= 1'b0;
      m_axi_awaddr  <= '0;
      m_axi_awlen   <= '0;
    end else if (can_issue) begin
      m_axi_awvalid <= 1'b1;
      m_axi_awaddr  <= curr_addr;
      m_axi_awlen   <= 8'(burst_beats - 5'd1);
    end else if (m_axi_awready) begin
      m_axi_awvalid <= 1'b0;
    end
  end
  assign m_axi_awsize  = 3'b011;   // 8 bytes per beat
  assign m_axi_awburst = 2'b01;    // INCR
endmodule

Ordering: the W engine pops wq in order and streams burst_beats beats from the FIFO
with WLAST on the last, WSTRB from s_keep only on the packet's final beat, WVALID
driven from FIFO state alone (never from AWREADY). Because wq_push and the AW register
load in the same cycle, W order equals AW order with a single ID. The tracker advances
curr_addr, decrements remaining_beats/avail_beats and clears pkt_eof_seen when the
EOF beat is reserved, all on burst_commit.

M11Q19 · B3. (5 min) Completion and Ordering Hazard

(5 min) Completion & Ordering Hazard.
When s_last arrives, the frame may have been split across 5 AXI bursts. When is it safe
to assert cpl_valid to firmware (so firmware can read the packet or trigger an interrupt)?
How do you track the 5 BVALID responses, and what if burst #3 returns SLVERR?

Gemini Answer

GPT Answer

With AWID=0, B responses are ordered; this particular engine cannot legally receive out-of-order B for its own writes. Count accepted AW minus retired B; associate every burst with the packet and OR all error responses. Complete only after EOF/overflow-drain policy is resolved, every committed W beat is accepted, all AW/B obligations retire, and completion data is stored stably until cpl_ready. Burst #3 SLVERR makes the packet error sticky even if other bursts succeed. Define cpl_bytes_written carefully: accepted/attempted valid bytes are knowable; a failing AXI response may not reveal exactly which bytes reached DRAM. A successful B still relies on the platform's visibility/coherency contract before CPU consumption.

Claude Answer

cpl_valid means "the packet is in memory", so it waits for all B responses of the packet,
not for WLAST. On each commit push a 1-bit "last burst of packet" flag into a FIFO in AW
order; pop one flag per BVALID && BREADY (single ID, responses are in order). While
popping, OR bresp != OKAY into a sticky packet-error bit; when a popped flag is set,
emit cpl_valid with bytes_written and the error bit, then clear the bit. Burst 3 with
SLVERR: keep issuing the remaining bursts so the counters stay consistent, report
cpl_status_err = 1, firmware discards the buffer; optionally a mode bit that drains the
rest of the packet from the FIFO without AXI writes.

M11Q20 · B4. (5 min) Soft Reset and Drain

(5 min) Soft Reset & Drain.
Firmware issues a soft reset (soft_rst_req) while a packet is mid-transfer. Design the
quiescence handshake (soft_rst_req → soft_rst_ack) so the AXI bus never violates
protocol.

Gemini Answer

GPT Answer

Stop admitting descriptors and new burst commitments; preserve any AW already offered even if not yet accepted, and finish all offered W beats. Drain B responses and consume/discard the unfinished incoming packet to a defined boundary, or handshake source cancellation. Hold reset acknowledgment until no issued/offered transaction or completion obligation remains and the source is quiesced. Then clear local state/advance epoch. A stalled fabric can prevent drain indefinitely; use the SoC's explicit timeout/recovery protocol if one exists.

Claude Answer

On soft_rst_req: (1) stop accepting descriptors and stop committing bursts; (2) let the W
engine finish any burst already committed — store-and-forward guarantees its beats are in
the FIFO, so this always completes; (3) hold BREADY = 1 and wait until outstanding == 0,
awvalid == 0 and the burst queue is empty; (4) drain the input stream (s_ready = 1,
discard to s_last) so the source isn't wedged; (5) assert soft_rst_ack, then clear
internal state. The AXI output registers are only reset after step 3, so the fabric never
sees a VALID vanish before its handshake.

Part C — Your questions (0:55–1:00)

M11Q21 · C. Questions for the interviewer

Gemini Answer

  1. "Does the SoC fabric here enforce strict power-of-two burst alignments or cache-line sizing (e.g., 64-byte bursts) in addition to the standard 4 KB AXI rule?"
  2. "How is bus hang recovery / timeout monitoring handled at the IP boundary—do masters include a local watchdog or rely on the SoC interconnect timeout slave?"
  3. "Do your DMA engines use physical addresses directly, or interface with an SMMU / IOMMU via AXI AWPROT/AWUSER stream IDs?"

GPT Answer

What coherency/doorbell ordering contract applies? What are the fabric outstanding/response limits? How is IP soft-reset quiescence tested?

Claude Answer

  1. Which fabric is used at SoC level (Arm NI, Arteris, custom NoC) and how are
    outstanding-transaction budgets allocated per IP?
  2. What is the SoC's rule for bus quiescence on block-level soft reset, and who verifies it?
  3. Is early write response allowed for DMA descriptor traffic, and how do firmware barriers
    map to the fabric?

Additional notes

Notes. Material not tied to a question

Gemini Answer

No answer in gemini_answer.md.

GPT Answer

Arm AMBA AXI and ACE protocol specification, IHI 0022H.

Claude Answer

No answer in claude_answer.md.