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Round 04 — Combined answers (Gemini · GPT · Claude)

Contents

• 0. Resume probe
  • M4Q1 · "80% fewer gates and 90% lower power. Walk me through the…
• Part A — Rapid-fire Q and A (0:05–0:20)
  • M4Q2 · A1. Break dynamic power into its terms. For a MAC that is idle…
  • M4Q3 · A2. Leakage: which three knobs reduce it, and which of them are…
  • M4Q4 · A3. ICG-based clock gating vs. an enable mux on the D input:…
  • M4Q5 · A4. What is operand isolation and when does it beat clock gating?
  • M4Q6 · A5. How does a synthesis tool estimate power without a…
  • M4Q7 · A6. Reading an area report: what do you look at first to decide…
  • M4Q8 · A7. A 1500-entry case statement producing a 12-bit value: what…
  • M4Q9 · A8. Resource sharing: give an RTL pattern where the tool will…
  • M4Q10 · A9. FSM encoding (binary / one-hot / gray): what does each buy…
  • M4Q11 · A10. Ungrouping / boundary optimisation: what does it enable,…
  • M4Q12 · A11. Multi-Vt: what is the typical split, who decides it, and…
  • M4Q13 · A12. Power domains / UPF: name the four cell types you must…
  • M4Q14 · A13. You want to prove the new design is smaller than the old…
  • M4Q15 · A14. "90% lower power by synthesis estimate" — give two reasons…
• Part B — Deep dive: factor the NDBPS lookup (0:20–0:55)
  • M4Q16 · B1. Legality
  • M4Q17 · B2. Factored datapath
  • M4Q18 · B3. Estimate
  • M4Q19 · B4. Power
  • M4Q20 · B5. Prove it
  • M4Q21 · B6. Timing and reuse
• Part C — Your questions (0:55–1:00)
  • M4Q22 · C1. Questions for the interviewer

0. Resume probe

M4Q1 · "80% fewer gates and 90% lower power. Walk me through the before/after measurement setup, and tell me what the number would have been at the slow corner."

Gemini Answer

• Before/After Measurement Setup:
  • Both designs (the legacy ~1500-entry flat case table vs. the redesigned algebraically factored N_SD × N_BPSCS × N_SS × R module) were synthesized standalone and in-context inside the Tx length-parameter hierarchy using Design Compiler / Genus against the exact same 5 nm/7 nm standard-cell library, same target clock constraint, same wireload/physical PLE model, and set_ungroup false on the module boundary so gates could not bleed across hierarchy.
  • 80% gate reduction: Came from replacing the 1500-row sum-of-products PLA (~9,000 combinational gates) with tiny 8-entry / 14-entry base LUTs plus a small shift-add/divide-by-3 circuit (~1,400 gates).
  • 90% power reduction: Measured via synthesis power reporting (report_power) combining (1) the $5\times$ reduction in internal node capacitance and glitching across deep PLA trees, and (2) adding input operand isolation / enable gating so the combinational cone only toggles on cycles when a rate lookup is actually requested (rate_req_valid), rather than toggling on every background change of the shared bus.
  • Slow (SS, low-V, high-T) vs. Typical/Fast corner: Gate count is almost identical at the slow corner (within ~3–5% from buffer/drive-strength sizing because the factored path easily meets timing without LVT/upsizing), whereas leakage power scales up with high temperature at the ML/SS-high-T corner in exact proportion to the 80% cell-area reduction.

GPT Answer

"For a 1x1 cost-down design I redesigned the NDBPS lookup, reducing gates by 80% and estimated power by 90% relative to the original, by synthesis. Those are block-level synthesis results, not measured silicon power. I would bring the actual baseline, library, corner, constraints, activity assumptions, and reports before quoting a corner-specific result." The resume does not identify those measurement settings or the implementation technique.

Claude Answer

Template (replace the corner/tool names with the real ones):

"Both numbers are module-level Design Compiler runs of the old and new ndbps_lut with
identical scripts: same library and corner, same SDC and clock, same tool version, same
hierarchy (flat, no ungroup differences), pre-DFT, clock gating enabled in both. 'Gates' is
NAND2-equivalent cell area from the area report, not cell count. Power is the DC/PrimeTime
PX estimate with the same SAIF from the module-level rate-matrix testbench, so the activity
is identical and representative of real per-PPDU traffic; it is dynamic power of the block
only, no clock tree, and I say that on the slide. At the slow corner the area ratio barely
moves because the structure is the same, and the dynamic-power ratio also holds; what
changes is the absolute numbers and the leakage share, so the total power ratio would be
a bit less than 90% at a hot, leaky corner where leakage of the remaining cells shows up."

Part A — Rapid-fire Q and A (0:05–0:20)

M4Q2 · A1. Break dynamic power into its terms. For a MAC that is idle 95% of the time, which term dominates and what does that imply for where you optimise?

Gemini Answer

• Terms:$$P_{\text{dyn}}=\alpha \cdot C_{\text{load}}\cdot V_{DD}^2\cdot f_{\text{clk}}+I_{\text{sc}}\cdot V_{DD}$$(switching power + internal short-circuit crowbar power; total power adds $P_{\text{leak}}=I_{\text{leak}}\cdot V_{DD}$).
• 95% idle MAC: Un-gated clock-tree switching ($\alpha =1.0$ every cycle on clock buffers/ICG inputs) and static leakage dominate!
• Implication: Optimizing datapath multiplier toggles buys almost nothing; you must apply architectural root clock gating (shutting off the clock tree to the entire Tx/Rx sub-blocks when idle) and UPF power gating / SRAM Deep Sleep during idle intervals.

GPT Answer

Switching power is approximately alpha*C*V^2*f, plus internal/short-circuit power; leakage is separate. At 95% idle, ungated clock power or leakage may dominate, but measure it. Target clocks, idle input toggles, and retention/power states according to that breakdown.

Claude Answer

P = α·C·V²·f (switching) + short-circuit + leakage (I_leak·V). At 95% idle the
switching term of the datapath is small; what's left is the clock tree (α ≈ 1 on every
clock pin) and leakage. So optimise at the root: hierarchical clock gating that stops whole
subtrees, and power gating of idle domains, rather than shaving datapath toggles.

M4Q3 · A2. Leakage: which three knobs reduce it, and which of them are available to an RTL engineer?

Gemini Answer

1. Multi-$V_t$ cell selection (HVT vs. SVT/LVT): Chosen by synthesis/PD, indirectly controlled by RTL: when RTL has generous timing slack (fewer logic levels), the tool maps 95%+ of gates to low-leakage HVT cells instead of leaky LVT cells.
2. Gate count / SRAM macro count reduction: Directly controlled by RTL architecture (e.g., factoring LUTs, sharing buffers, using 1RW instead of 2RW SRAMs).
3. Power gating (MTCMOS header/footer switches) & SRAM sleep modes (LS/DS/SD): Controlled by RTL power-management FSMs and UPF definitions.

GPT Answer

Higher-Vt cells, power gating, and reduced device/cell area reduce leakage; supply/bias choices can also matter. RTL directly influences area and idle architecture; library selection and power intent require implementation collaboration.

Claude Answer

Higher-Vt cells, power gating (cut supply), lower voltage / body bias (plus longer
channel cells). The RTL engineer controls area (fewer cells leak less), the power-gating
structure (domain partition, isolation, retention), and critical-path length so PD can swap
LVT back to HVT.

M4Q4 · A3. ICG-based clock gating vs. an enable mux on the D input: area, power, and timing consequences. When does the tool refuse to insert an ICG?

Gemini Answer

• Area: One ICG cell (~3–4 gate equivalents) amortizes across a 32- or 64-bit register bank and allows removing the 2:1 feedback mux inside every flip-flop (smaller non-scan/scan DFFs).
• Power: An ICG stops the clock signal from toggling inside all 64 flip-flops (saving ~50–70% of register clock-pin dynamic power); a D-input recirculation mux still clocks all 64 flip-flops every cycle!
• Timing: ICG trades removes D-pin mux setup delay in exchange for an enable-to-ICG setup check against the falling (or rising) clock edge.
• When synthesis refuses to insert an ICG: When the register bank width is below min_bitwidth (e.g., < 3 or < 4 bits where ICG overhead > savings), when en is timing-critical and fails ICG setup, or when the flop has complex asynchronous/synchronous reset interactions that cannot be factored into a clean synchronous load enable.

GPT Answer

An enable mux prevents data updates but still clocks the flop. An ICG suppresses clock-tree/flop switching, at the cost of a gate, control timing, test enable, and minimum group size. Unsupported enable logic, unsafe timing, small groups, or policy restrictions may prevent insertion.

Claude Answer

ICG: one cell per register bank, stops clock-tree and flop-internal clock toggling
(the big win), adds an enable-to-ICG setup check and a latch in the clock path. Enable mux:
one mux per bit, flops still clocked every cycle, saves nothing on the clock tree, and adds a
level to the D path. The tool refuses below the minimum bank width, when the enable isn't a
pure synchronous enable (mixed with reset or async terms), when the enable cone is
excluded by constraint, or when the flops are on the critical path and the extra setup
check would fail.

M4Q5 · A4. What is operand isolation and when does it beat clock gating?

Gemini Answer

• What it is: Inserting an AND/OR gate (or transparent latch/register enable) at the inputs of a large purely combinational block (like a wide multiplier, CRC tree, or NDBPS decoder) to freeze its inputs when its output will not be sampled downstream.
• When it beats clock gating: When the upstream registers must keep toggling every cycle for other consumers, so those registers cannot be clock-gated, yet the expensive combinational cone only needs to produce a valid result on 5% of cycles.

GPT Answer

Operand isolation holds inactive inputs constant so a combinational cone stops toggling. It can beat clock gating when upstream inputs still toggle into a large inactive combinational block; often use both. Place the isolation before the expensive cone.

Claude Answer

Holding the inputs of a combinational cone stable (AND/latch) when its output
is unused, so a multiplier doesn't churn. Beats clock gating when the cone is combinational
and fed from registers that must keep toggling for other consumers, or when inputs change
every cycle but the result is consumed rarely.

M4Q6 · A5. How does a synthesis tool estimate power without a simulation? What is a SAIF/VCD-based estimate, and which of the two numbers do you put on a slide?

Gemini Answer

• Vectorless (without sim): The tool assumes a default static probability (e.g., 0.5) and toggle rate (e.g., 0.1 or 0.2 toggles per clock) on primary inputs/flops and propagates probabilities through Boolean gates.
• SAIF (Switching Activity Interchange Format) / VCD: annotates every net and register with real toggle counts and 1/0 duty cycles captured from a representative simulation test (e.g., idle beacon listen vs. max-throughput UDP).
• Which goes on a slide: Always SAIF-annotated power on stated workloads (e.g., "Active Tx MU-PPDU" vs. "Rx Listen"), explicitly noting whether it is pre-layout (wireload/PLE) or post-P&R (extracted parasitics + real CTS clock tree).

GPT Answer

Vectorless estimates assume toggle probabilities; SAIF/VCD-based analysis uses simulated activity, with coverage and annotation limits. Present activity-based estimates when representative, and label workload/corner/coverage. Never present either as measured silicon power.

Claude Answer

Without a simulation: static probability and toggle rate defaults at primary inputs
(say 0.5 / 0.1) propagated probabilistically through the netlist, usually ignoring glitches
and the clock tree. SAIF/VCD: real activity from a representative test applied net by net.
The slide gets the SAIF number, with the traffic scenario, corner and whether the clock
tree is included written on it.

M4Q7 · A6. Reading an area report: what do you look at first to decide whether a change actually helped — total cell area, combinational vs. sequential split, or something else?

Gemini Answer

1. Sequential vs. Combinational vs. Macro/Memory split at each hierarchy level.
2. Flop count (Number of sequential cells): Verify no registers were accidentally constant-propagated away (0 area because a bug tied valid to 0!) or duplicated unexpectedly.
3. LVT/SVT/HVT distribution and buffer/inverter area: Check that a smaller combinational gate count didn't come at the cost of forcing the tool to swap HVT cells to LVT to meet timing.

GPT Answer

First compare the same functionality and scope at the same timing target. Then inspect total mapped area, sequential/combinational split, buffers/clock gates, and slack. Check whether logic moved across a reporting boundary or a smaller design missed timing.

Claude Answer

Sequential cell count and area first: if the flop count moved, functionality or
pipelining changed, or something got optimised away. Then combinational area by hierarchy
to localise the change, then check nothing was constant-propagated out because of an
unconnected output or a tied input. Total cell area last, and only if both runs used the
same constraints.

M4Q8 · A7. A 1500-entry case statement producing a 12-bit value: what does synthesis build, and why might it be far from minimal?

Gemini Answer

• Synthesis treats a flat truth table as 12 independent Boolean functions of the 15-bit input vector and runs two-level heuristic logic minimization (Espresso-style SOP factoring).
• Espresso only looks for Boolean cube overlaps (Hamming-1 product terms); it cannot discover arithmetic factorization ($A\times B\times C$), because binary multiplication mixes bits across all positions nonlinearly.

GPT Answer

A case table becomes optimized decode/mux/Boolean logic, or a ROM where mapping supports it. A generic optimizer may miss algebraic structure across 1500 entries; repeated decodes and wide muxing can dominate.

Claude Answer

A ROM/PLA-style sum-of-products after heuristic two-level minimisation, then
technology-mapped. It is far from minimal because the tool sees a 13-input, 32-output
boolean function with no idea that it is a product of small factors; illegal combinations
become explicit values instead of don't-cares; and the result depends on case-item order
and default handling.

M4Q9 · A8. Resource sharing: give an RTL pattern where the tool will share a multiplier and one where it cannot, even though mathematically it could.

Gemini Answer

• Will share:

  always_comb begin
    if (sel) y = a * b;
    else     y = c * d;
  end
  

  (Mutually exclusive branches of the same if/case driving the same target variable with similar widths—synthesis transforms this into (sel ? a : c) * (sel ? b : d)).
• Cannot share automatically: When the two multiplies are active in different pipeline stages (temporal sharing across cycles requires an explicit FSM/mux), or exist in separate modules across a dont_touch/hierarchical boundary, or both products are needed in the same cycle.

GPT Answer

(sel ? a : c) * b exposes one shared multiplier. Two independent products required simultaneously cannot use one single-cycle multiplier without scheduling or a faster internal clock. Mutually exclusive expressions can sometimes be shared automatically, but verify the mapped netlist.

Claude Answer

Shareable: if (sel) y = a*b; else y = c*d; — mutually exclusive branches, same
width/signedness → one multiplier with muxed operands. Not shareable: y = a*b + c*d
(both needed at once), different widths or signedness, a register between the two uses,
the two multiplies in different always blocks, or when the shared version fails timing.

M4Q10 · A9. FSM encoding (binary / one-hot / gray): what does each buy in area, speed, and power, and how do you stop the tool from re-encoding when you need LEC to pass?

Gemini Answer

• Binary: $\lceil {\log }_{2}N\rceil$ flops (minimum sequential area), deeper next-state/output decode logic, multiple bits toggle per transition.
• One-Hot: $N$ flops, fastest speed (1-bit state compare, tiny decode logic), exactly 2 flops toggle per transition.
• Gray: $\lceil {\log }_{2}N\rceil$ flops, exactly 1 flop toggles on linear state sequences (lowest glitch/switching power, safe for async pointer sampling).
• Stopping tool re-encoding for LEC: Use synthesis attributes ((* fsm_encoding = "none" *) or set_fsm_preserve_state_registers true / compile_ultra -no_autoungroup -no_seq_output_inversion), or pass the .svf guidance file to Conformal LEC so it knows the state mapping.

GPT Answer

Binary uses few state flops; one-hot often simplifies decode at greater clock/reset cost; Gray can reduce transitions for suitable state sequences. No encoding wins universally. Use supported preservation settings and compatible equivalence setup where exact encoding is required; LEC need not fail merely because encoding changes.

Claude Answer

Binary: fewest flops, denser next-state logic. One-hot: simplest decode, fastest,
N flops. Gray: one bit toggles per transition, lowest state-register switching. To keep LEC
simple: disable FSM extraction/re-encoding (set_fsm_encoding/-fsm_extract none or the
Genus equivalent) and code states as explicit localparam values so the state flops map
1:1. If re-encoding is allowed, LEC needs the FSM mapping file.

M4Q11 · A10. Ungrouping / boundary optimisation: what does it enable, what does it break (think ECOs, LEC, hierarchical timing budgets)?

Gemini Answer

• What it enables: Constant propagation across module ports, merging duplicate gates across sub-block boundaries, and trimming unused port bits (~5–15% area/timing improvement).
• What it breaks:
  1. Post-freeze Metal/Gate ECOs: Internal module port nets disappear or get inverted/merged, making hand ECOs much harder to locate.
  2. Hierarchical LEC & attribution: Per-module area/power tracking and hierarchical black-box LEC fail when boundaries dissolve.

GPT Answer

Boundary optimization exposes constants, sharing, and cross-module simplification. It complicates hierarchical matching, ECO locality, names, and independent timing budgets. Preserve selected architectural boundaries rather than disabling optimization everywhere.

Claude Answer

Enables cross-boundary constant propagation, dead-logic removal through ports,
sharing and cross-boundary timing optimisation. Breaks: swapping a sub-block netlist in an
ECO, hierarchical LEC (compare points at the boundary vanish), per-block timing budgets and
per-block DFT chains. Keep the boundaries you'll need for ECO/LEC/budgets; ungroup glue.

M4Q12 · A11. Multi-Vt: what is the typical split, who decides it, and why does an RTL change affect it?

Gemini Answer

• Typical split: ~80–90% HVT (high threshold, low leakage, slower), ~10–18% SVT, and <2–5% LVT/ULVT (restricted to critical paths).
• Who decides: Synthesis and Physical Design tools during timing optimization.
• How RTL affects it: If an RTL path has 28 levels of logic instead of 18, the tool swaps hundreds of gates along that cone from HVT to LVT to close setup timing, multiplying leakage power on that block by $5\text{–}10\times$.

GPT Answer

There is no universal multi-Vt percentage. Implementation chooses the mix to meet timing/leakage goals. Shorter RTL paths create slack for higher-Vt cells; added mux depth can force lower-Vt cells.

Claude Answer

Typically 80–90% HVT/SVT and 5–20% LVT/ULVT on critical paths; PD decides during
leakage recovery after timing closure. An RTL change that shortens the critical path or
cuts a high-fanout net lets PD swap LVT back to HVT, so leakage follows RTL timing quality.

M4Q13 · A12. Power domains / UPF: name the four cell types you must think about when a block can be powered off, and what the RTL author must provide for each.

Gemini Answer

1. Isolation cells (ISO): Clamp signals crossing from a power-gated domain to an always-on domain to 0 or 1. RTL provides: glitch-free iso_en control asserted before power-down.
2. Retention flip-flops (RFF): Keep state in a balloon latch during power-off. RTL provides: save strobe before power-off and restore strobe after power-on (while clock is gated).
3. Level shifters (LS): Translate voltage swings between $V_{DD1}$ and $V_{DD2}$ domains. RTL provides: clean domain boundary partitioning.
4. Power switches (Header/Footer MTCMOS): Gate $V_{DD}$ / $V_{SS}$. *RTL provides:*daisy-chained pwr_req / pwr_ack power controller FSM sequencing reset, clock gate, save, iso_en, and switch enable.

GPT Answer

Think isolation, level shifters, retention flops, and power switches. RTL/architecture supplies safe clamp values, voltage crossings, retained state, and sequencing/control intent; UPF and implementation describe/insert the physical structures. Reset/restoration and always-on control must also be specified.

Claude Answer

Isolation cells (RTL: isolation enable and clamp value, sequenced before power
off), level shifters (RTL: know and keep the boundary clean), retention flops (RTL:
save/restore sequence and which registers), power switches (RTL: the power-sequence
controller: isolate → save → switch off, and acks on the way up). Always-on buffers for
signals that cross the off domain.

M4Q14 · A13. You want to prove the new design is smaller than the old one. List the conditions the two synthesis runs must share for the comparison to be valid.

Gemini Answer

• Identical process technology library and PVT corner(s).
• Identical clock period, clock uncertainty, and input/output delay constraints (.sdc).
• Identical tool version, compile_ultra effort flags, and hierarchy preservation settings (-no_autoungroup).
• Identical switching activity profile (same SAIF stimulus or explicit input toggle rates).

GPT Answer

Match library/PVT, tool version/options, timing and I/O constraints, parameters, hierarchy scope, power intent, physical assumptions, scan state, and activity workload. Establish equivalence and compare timing as well as area/power.

Claude Answer

Same library and corner, same SDC/clock/I/O constraints, same tool version and
scripts, same hierarchy and ungroup settings, same DFT state, same clock-gating settings,
same physical mode (wire-load or placement-aware), same definition of "gates" (NAND2
equivalents vs cell count), and the same boundary of what is counted.

M4Q15 · A14. "90% lower power by synthesis estimate" — give two reasons that number could be wrong in silicon, in either direction.

Gemini Answer

1. Over-estimated in synthesis: If the parent hierarchy already clock-gates or operand-isolates the inputs when the MAC is idle, the baseline block was already consuming near-zero dynamic power 95% of the time in silicon, so chip-level savings are smaller than standalone vectorless block estimates.
2. Under-estimated in synthesis: Pre-layout synthesis ignores long physical wire capacitances and multi-input gate glitch propagation delays across 9,000 gates of deep PLA logic, so the real silicon dynamic energy reduction during active bursts can be even larger.

GPT Answer

Real traffic/idle behavior may differ from assumed toggles; routed capacitance, glitches, CTS, voltage, temperature, and leakage may differ from pre-layout estimates. Savings may increase or decrease depending on these factors.

Claude Answer

Too optimistic: default activity instead of real traffic, or the old block was
already clock-gated upstream so its real power was never 100%. Too pessimistic/wrong the
other way: clock tree, glitch power in deep SOP logic and wire cap are missing from the
estimate, so the real saving from killing a glitchy 9k-cell cone can be larger than the
estimate; and at a hot corner leakage of the remaining cells dilutes the total ratio.

Part B — Deep dive: factor the NDBPS lookup (0:20–0:55)

The legacy block computes N_DBPS (data bits per OFDM symbol) and N_CBPS (coded bits per
symbol) with a flat lookup:

inputs:  mcs[3:0]    (0..13)
         nss[2:0]    (1..8 encoded as 0..7)
         ru[3:0]     (RU/BW size index: 26,52,106,242,484,996,2x996,4x996 tones ...)
         dcm         (dual-carrier modulation, halves data rate for MCS 0/1/3/4)
outputs: n_dbps[15:0], n_cbps[15:0], valid (0 for illegal combos)

Implemented as case ({mcs,nss,ru,dcm}) with ~1500 explicit entries generated by a script
from the 802.11 rate tables. Synthesis gives ~9 k cells. You must cut it hard for a 1×1
cost-down die.

Reference formulas (802.11ax/be):

N_SD(ru)        : data subcarriers per RU   (26-tone:24, 52:48, 106:102, 242:234, 484:468,
                                             996:980, 2x996:1960, 4x996:3920)
N_BPSCS(mcs)    : bits per subcarrier       (1,2,2,4,4,6,6,6,8,8,10,10,12,12 for MCS 0..13)
R(mcs)          : code rate                 (1/2,1/2,3/4,1/2,3/4,2/3,3/4,5/6,3/4,5/6,3/4,5/6,3/4,5/6)
N_CBPS = N_SD * N_BPSCS * N_SS
N_DBPS = N_CBPS * R
DCM: halves N_BPSCS effectively (only valid for MCS 0,1,3,4)

M4Q16 · B1. Legality

1. (5 min) Legality. Which combinations are illegal (e.g., MCS 12/13 at small RUs, DCM
   with MCS 2)? How would you represent legality compactly rather than as 1500 case items?

Gemini Answer

Instead of encoding legality in 1,500 rows, legality in 802.11ax/be/bn is the conjunction of four orthogonal rules (~40 gates total):

// 1. Range checks
wire mcs_range_ok = (mcs <= 4'd13);
// 2. DCM is only legal for MCS ∈ {0, 1, 3, 4} and NSS ∈ {1, 2} (encoded nss <= 1) and not 4096-QAM
wire dcm_ok       = !dcm || ((mcs == 4'd0 || mcs == 4'd1 || mcs == 4'd3 || mcs == 4'd4) && (nss <= 3'd1));
// 3. Small RU restrictions: MCS 10/11 require RU >= 26 (always true), MCS 12/13 (4096-QAM) if restricted,
//    plus classic 802.11ac/ax integer N_DBPS exclusion (only exists in VHT 20MHz MCS9 NSS != 3,6; in HE/EHT all are integer!)
wire ru_mcs_ok    = (ru <= 4'd7); // valid RU index
assign valid      = mcs_range_ok && dcm_ok && ru_mcs_ok;

GPT Answer

Legality: decode field ranges, actual NSS=encoded_nss+1 using four bits, DCM eligibility, and standard/version/RU-specific restrictions as compact predicates or small masks. DCM with MCS 2 is excluded by the exercise. Do not invent a blanket small-RU restriction for MCS 12/13: verify the exact PHY format and standard revision against approved tables. Keep legality separate from the numeric computation.

Claude Answer

Rules, not entries: DCM only with MCS ∈ {0,1,3,4} and nss ≤ 2; MCS 12/13 only at RU ≥ 242
and never with DCM; MCS 10/11 excluded at the smallest RUs per the table; mcs ∉ 0..13
or ru beyond the defined indices → invalid. Represent as an 8-entry ROM indexed by ru
that returns a 14-bit "allowed MCS" mask, ANDed with the DCM and nss rules: tens of gates.

M4Q17 · B2. Factored datapath

2. (10 min) Factored datapath. Design the arithmetic structure for N_CBPS and N_DBPS.
   Deal with the fractional code rate exactly (no floating point, no divider): show how to
   compute N_CBPS * R for R ∈ {1/2, 2/3, 3/4, 5/6} using shifts, adds and tiny multipliers
   so that the result is bit-exact with the table.

Gemini Answer

We use the exact 802.11 physical factorization:

Trick to make $\times R\in \{1/2,2/3,3/4,5/6\}$ 100% bit-exact without a divider:
Notice that every $N_{\text{SD}}(\text{ru})$ in 802.11ax/be/bn is even, and for every MCS with $R=2/3$ or $R=5/6$, $N_{\text{BPSCS}}\in \{6,12\}$ is an exact multiple of 6!
Therefore, define pre-divided sub-carrier bits:

• Instead of multiplying by $N_{\text{BPSCS}}$ and then dividing by $3$ or $6$, note that:$$K_{\text{CBPS}}(\text{mcs})=N_{\text{BPSCS}}(\text{mcs})\in \{1,2,2,4,4,6,6,6,8,8,10,10,12,12\}$$And for $N_{\text{DBPS}}$, observe that $N_{\text{SD}}(\text{ru})$ is always divisible by 2 (N_SD_half = N_SD >> 1 $\in \{12,24,51,117,234,490,980,1960\}$), and for every MCS:$$N_{\text{BPSCS}}(\text{mcs})\times R(\text{mcs})\times 2=M_{\text{DBPS}}(\text{mcs})\in \{1,2,3,4,6,8,9,10,12,15,18,20\}$$Wait—look at that identity:
  • MCS 0 ($1\times 1/2\times 2$) = 1
  • MCS 1 ($2\times 1/2\times 2$) = 2
  • MCS 2 ($2\times 3/4\times 2$) = 3
  • MCS 3 ($4\times 1/2\times 2$) = 4
  • MCS 4 ($4\times 3/4\times 2$) = 6
  • MCS 5 ($6\times 2/3\times 2$) = 8
  • MCS 6 ($6\times 3/4\times 2$) = 9
  • MCS 7 ($6\times 5/6\times 2$) = 10
  • MCS 8 ($8\times 3/4\times 2$) = 12
  • MCS 9 ($8\times 5/6\times 2$) = $40/3$ (only non-integer, handled by N_SD / 3 or exact N_SD_div6 table!)
    Even better: Because ru has only 8 entries, store a second tiny 8-entry table N_SD_div3[ru] (or for RU=26/106 where $N_{\text{SD}}\in \{24,102,234,468\}$ is divisible by 6, and for RU=996 where $N_{\text{SD}}=980$, compute div3 via exact constant multiply (x * 16'h5556) >> 18).
    Then:
  1. 8-entry LUT N_SD[ru] (12 bits).
  2. 14-entry LUT N_BPSCS[mcs] (4 bits), shifted right by 1 if dcm.
  3. N_CBPS_1ss = N_SD * N_BPSCS ($12\times 4$-bit shift-add = two 14-bit adders!).
  4. N_CBPS = N_CBPS_1ss * (nss + 1) ($16\times 4$-bit shift-add = two 16-bit adders).
  5. N_DBPS: apply exact rate factor $R\in \{1/2,2/3,3/4,5/6\}$:
     • div2 = N_CBPS >> 1
     • div4 = N_CBPS >> 2
     • div6 = (N_CBPS >> 1) * 17'hAAAB >> 17 (exact integer division by 3 for all 16-bit multiples of 3!)
     • Mux by rate:
       • $1/2\to \text{div2}$
       • $3/4\to \text{div2}+\text{div4}$
       • $2/3\to \text{div6}\ll 1$
       • $5/6\to (\text{div6}\ll 2)+\text{div6}$

GPT Answer

Structure: decode N_SD, modulation bits, and rate numerator/denominator; use shift/add choices for small constants and a small NSS multiplier. Form CBPS=NSD*BPSCS*NSS, then apply the specified DCM and coding-rate rules. Preserve rational precision until the spec's defined rounding point. For an exactly divisible C: half=C>>1; three-quarters=(C>>2)*3 when C is divisible by 4; two-thirds=2*(C/3) when divisible by 3; five-sixths=5*(C/6) when divisible by 6. Cancel denominator factors against NSD/BPSCS/NSS before multiplying. A small RU/MCS/DCM table of precomputed exact factors, or fixed reciprocal/shift/add division with proven correction, removes a runtime variable divider.

Width/spec trap: the exercise's unrestricted maximum CBPS is 3920*12*8=376320, requiring 19 bits; 16-bit outputs overflow. Also, its simplified formulas can yield fractions, e.g. 980*8*5/6. Resolve legality, units, and rounding against the golden reference rather than silently truncating. Reordering a truncating divide and NSS multiply is not generally equivalent.

Claude Answer

• N_SD: 8-entry × 12-bit ROM. N_BPSCS: 14-entry × 4-bit ROM. Rate select
  (num,den) from mcs[0] plus a 3-way class: 2 bits.
• N_CBPS = (N_SD × N_BPSCS × (nss+1)) >> dcm. The 12×4 multiply is small; × (nss+1)
  is a shift-add over 1..8; N_SD is always even so the DCM halving is exact.
• Code rate, exactly: all four rates are integers when scaled by 12 (12R ∈ {6, 8, 9, 10}),
  so n_dbps_x12 = N_CBPS × 12R is one shift-add
  (x<<2 + x<<1, x<<3, x<<3 + x, x<<3 + x<<1) and never divides. Then
  n_dbps = n_dbps_x12 / 12: /4 is a shift, and /3 is absorbed into the ROMs — store
  N_BPSCS/3 for MCS 5/7/13 (6, 6, 12) and N_SD/3 for the RUs divisible by 3.
• The catch I'd raise: 980 × 8 × 5/6 is not an integer. 802.11ax really does have
  fractional N_DBPS for MCS 9/11 at 996-class RUs, so the generated table has a rounding
  convention. I'd match that convention explicitly, or better, keep the ×12 form and let
  the consumer (round 02's ceil-divide) scale its numerator by 12 so the whole path is
  exact integer arithmetic. Also n_cbps[15:0] can't hold 1960 × 10 × 8; the port is
  19 bits for 802.11be.

M4Q18 · B3. Estimate

3. (5 min) Estimate. Estimate gate count for your structure (tables, multipliers, adders,
   muxes) and compare to the 9 k baseline. Which piece dominates?

Gemini Answer

• N_SD[0..7] 8×12 LUT: ~40 gates
• N_BPSCS[0..13] + rate code 14×6 LUT: ~50 gates
• N_SD * N_BPSCS ($12\times 4$ shift-add, since $N_{\text{BPSCS}}\in \{1,2,4,6,8,10,12\}$ has at most two non-zero bits!): 1 adder + mux (~90 gates)
• $\times N_{\text{SS}}$ ($\times 1..8$, at most two non-zero bits): 1 adder + mux (~110 gates)
• Exact div3 constant multiplier (* 0xAAAB >> 17) + rate adder: ~350 gates
• Legality check + output muxes: ~80 gates
• Total: ~720–950 gates vs. 9,000 gates ($\mathbf{>}\mathbf{88}\mathbf{\%}$ gate reduction), dominated by the div3 constant multiplier.

GPT Answer

Estimate: replace a wide flat decoder with small tables, narrow constant arithmetic, and NSS scaling; for the 1x1 derivative, constant-propagate NSS=1. I would budget on the order of hundreds to a few thousand equivalent gates initially, then measure. Mux/arithmetic structure and library mapping decide the result; a precise gate count without synthesis would be invented.

Claude Answer

The multiplier and the × nss adder chain dominate; the ROMs are noise. That is a ~92%
cut, consistent with the 80% I measured on the real block (which carries extra outputs).

M4Q19 · B4. Power

4. (5 min) Power. This block is evaluated once per PPDU but sits in a clock-always-on
   region. Where does its power go, and what structural change gets you a large power
   reduction independent of the area reduction?

Gemini Answer

• Gate the inputs to the combinational datapath using an ICG-gated input register stage (or operand isolation AND gates qualified by lookup_req_valid). Since N_DBPS is only needed once at the start of each PPDU (or 1–8 cycles for MU), freezing the inputs prevents the multiplier/adder cone from toggling during the remaining 99.9% of clock cycles.

GPT Answer

Power: isolate or capture request inputs only when the block is invoked; hold them stable while idle. Gate pipeline registers with recognized enables/ICGs. An always-on clock region does not require the whole arithmetic cone to toggle continuously. Separate clock savings from area-related and operand-activity savings.

Claude Answer

Baseline burned power because mcs/nss/ru are shared registers that change every cycle
and 9k cells of glitchy SOP logic re-evaluated continuously. Structural fix: register the
inputs behind an ICG enabled by tx_start (or operand-isolate the cone) so the logic sees
one input change per PPDU and sits still otherwise. That is most of the 90%; the smaller,
shallower cone also has far less glitch power per evaluation.

M4Q20 · B5. Prove it

5. (5 min) Prove it. How do you prove the factored version equals the table for every
   legal input and produces valid=0 for every illegal input? What tool, what runtime, and
   what do you do about LEC when the structure has totally changed?

Gemini Answer

• Exhaustive simulation / Formal proof: The input space is only $4+3+4+1=12$ bits ($2^{12}=4,096$ total input combinations!). A directed SV testbench (or JasperGold / Conformal LEC) sweeps all 4,096 vectors in <10 ms, asserting factored_ndbps == legacy_ndbps && factored_ncbps == legacy_ncbps && factored_valid == legacy_valid.
• What happens in Conformal LEC: Because ndbps_lookup is a purely combinational module (or has identical input/output flops), Conformal compares the primary outputs (POs) directly as Boolean functions of the primary inputs (PIs) (12 inputs → 33 outputs). For a 12-input cone, BDD/SAT-based LEC proves 100% equivalence in under 1 second even though the internal gate structure is completely different! (Only if an illegal input vector previously had "don't-care" outputs that changed do you add a constraint add_pin_constraints or force illegal inputs to output 0 in both).

GPT Answer

Proof: build a combinational miter over old/new outputs and legality. The raw input space is only 16*8*16*2=4096 combinations, so exhaustive evaluation is practical too. Compare valid on all inputs and numeric outputs where the contract defines them, including illegal-output behavior if specified. Use formal/LEC with output-level matching rather than requiring internal register correspondence. Runtime should be measured, not promised. Sequentially pipelined versions need latency-aware equivalence or a transaction scoreboard.

Claude Answer

• Exhaustive simulation: the input space is 2^12 = 4096 vectors; drive every one through
  both the generated table and the factored block, compare n_dbps/n_cbps/valid. Seconds.
• Formal: Conformal/Formality on the two combinational modules. LEC maps primary outputs and
  flops as compare points, not internal structure, so a purely combinational rewrite needs no
  mapping work; it just proves the output cones equivalent. Seconds of runtime.
• A Python model of the spec formulas against the spec tables as the third leg, so the
  generated table itself is audited.

M4Q21 · B6. Timing and reuse

6. (5 min) Timing & reuse. The block's output now feeds the re-pipelined length-parameter
   path from round 02. Does your factored design fit in one 640 MHz cycle? If not, where do
   you cut? Can the same structure give you the reciprocal of N_DBPS for free?

Gemini Answer

• Fits in one 640 MHz cycle (1.56 ns)? LUT (2 levels) + ×N_BPSCS (4 levels) + ×N_SS (4 levels) + div3 + rate_add (10 levels) = ~20 levels of logic, which easily closes in one 640 MHz cycle in 5 nm! If tighter margin is desired, cut a pipeline register right after N_CBPS (10 levels + 10 levels).
• Free Reciprocal recip(N_DBPS): Yes! Since $1/N_{\text{DBPS}}=\frac{1}{N_{\text{SD}}}\times \frac{1}{N_{\text{BPSCS}}\cdot R}\times \frac{1}{N_{\text{SS}}}$, storing an 8-entry recip_N_SD[ru] LUT and a 14-entry recip_rate[mcs] LUT lets you compute the 36-bit reciprocal for Round 02's ceil-divider using a single small multiply!

GPT Answer

Timing/reuse: put rate/legality decode before arithmetic; cut between base-rate generation, NSS scaling, and quotient arithmetic as needed. Only synthesis and placement establish 640 MHz closure. The reciprocal is not free: a legal-divisor index can address a separate constant ROM, with additional area, precision, and timing cost.

Claude Answer

ROM (3 levels) → 12×4 mult (~12) → × nss adders (~10) → ×12R adder (~8) → mux: about
35 levels, marginal at 640 MHz (~30 budget). Cut after N_CBPS: stage 1 ROMs + multiply +
× nss, stage 2 rate scaling + legality + outputs. Reciprocal: 1/N_DBPS = 1/N_SD · 1/N_BPSCS · 1/(nss+1) · 1/R; the first three are tiny ROMs and 1/R is exact, so a second product
path gives a fixed-point reciprocal with two small multiplies — cheap, not free, and the
error compounds, so it needs ~2 guard bits per factor and relies on the ±1 correction
stage in the ceil-divide. That is the design I'd pair with round 02.

Part C — Your questions (0:55–1:00)

M4Q22 · C1. Questions for the interviewer

Gemini Answer

1. "Does the synthesis flow here run power-aware optimization using real SAIF activity vectors from DV regressions, or vectorless estimation?"
2. "How does the team balance module boundary preservation (for LEC/ECOs) against auto-ungrouping for PPA?"
3. "What is the UPF power-domain partitioning across the MAC—is there an always-on beacon/TSF island separate from the main Tx/Rx power domain?"

GPT Answer

Which traffic traces drive power signoff? How are before/after PPA runs normalized? Who owns MAC UPF and the legal-rate golden tables?

Claude Answer

1. Is there a SAIF-driven power flow at IP level, and which traffic profile is the
   reference for the MAC?
2. Who owns UPF for the MAC, and at what stage is the domain partition frozen?
3. How early is hierarchical vs. flat synthesis decided, and can an IP ask for a kept
   boundary for ECO reasons?