RTL Review

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Round 07 — Combined answers (Gemini · GPT · Claude)

0. Resume probe

M7Q1 · "Three post-freeze ECOs: tell me about the one you were least sure of, and how LEC convinced you."

Gemini Answer

Answer: The trickiest of my three post-freeze gate-level ECOs modified a multi-input state/abort qualification path where synthesis had already merged and inverted shared sub-expressions across two adjacent cones (using OAI22/NAND gates with inverted phase).
Why I was cautious: Touching an intermediate net in a hand-edited netlist risks unintentionally altering a second fanout cone that shared that inverted term.
How I proved it in Conformal LEC:
1. First, I ran Gate-to-Gate LEC (Pre-ECO Netlist as Golden vs. Post-ECO Netlist as Revised). Out of ~45,000 key points in the block, Conformal reported 44,999 Equivalent and exactly 1 Non-Equivalent (the single target flip-flop D cone I intended to modify)—proving 100% zero collateral damage to any other flop or output port.
2. Second, I updated the golden RTL with the 2-line fix and ran RTL-to-Gate LEC (Updated RTL as Golden vs. Post-ECO Netlist as Revised with .svf guidance and scan_en = 0), getting 0 Non-Equivalent key points across the entire block.

GPT Answer

"I implemented three post-freeze gate-level ECOs by hand and validated them using RTL-to-gate and gate-to-gate equivalence. I also own MAC RTL releases and backend coordination. For the specific ECO I was least certain about, I would explain its actual changed cone, counterexample/debug process, and timing/DFT checks; the resume does not document that story. LEC establishes implementation-to-reference equivalence, not whether the reference meets the specification."

Claude Answer

Template: "The one I trusted least touched a cone shared by two flops, so a one-cell
change could alter a second endpoint I hadn't meant to touch. What convinced me was not
the ECO itself but the gate-to-gate run: golden = signed netlist, revised = patched
netlist, and the non-equivalent list contained exactly the one endpoint I intended and
nothing else. Then the RTL-to-gate run against the updated RTL came back fully equivalent,
which closed the loop that the intended change was also the correct one. GLS of the
failing certification test was the third leg; LEC alone never tells you the reference was
right."

Part A — Rapid-fire Q and A (0:05–0:20)

M7Q2 · A1. Functional ECO vs. timing ECO vs. metal-only ECO: who initiates each, and what changes in which files (RTL, netlist, DEF, SDC)?

Gemini Answer

Functional ECO (Pre-Mask / Base-Layer allowed): Initiated by RTL/DV/SW to fix a logic bug after synthesis freeze. Changes: RTL (for reference), gate-level .v netlist, incremental placement/routing in .def (can add new standard cells if base layers aren't taped out), and .sdc only if new paths/clocks are added.
Timing / DRC ECO: Initiated by Physical Design / STA to fix setup, hold, or slew/capacitance violations. Changes: gate-level .v netlist and .def (buffer insertion, cell sizing, Vt swaps, useful skew); RTL does not change (Gate-to-Gate LEC must be 100% equivalent).
Metal-Only ECO: Initiated after base layers (diffusion/poly/contact) are frozen or in fab. Changes: only metal/via routing layers in .def and gate-level .v wiring by disconnecting tie-cells and wiring pre-placed spare cells (SPARE_*).

GPT Answer

Functional ECO changes behavior: usually updated RTL, patched netlist, implementation database/DEF, and constraints if needed. Timing ECO changes cells/buffers/routes, usually without changing functional RTL. Metal-only describes a physical restriction: reuse placed cells and change allowed interconnect layers; it can implement either kind. Design, PD, and program stakeholders own different approvals.

Claude Answer

Functional: raised by design/DV/SW/certification; changes RTL (reconciled later),
netlist, DEF, sometimes SDC. Timing: raised by PD/STA; netlist and DEF only (sizing,
buffering), SDC rarely. Metal-only: executed by PD with spare cells after base layers are
frozen; netlist plus routing layers in DEF, no new base-layer cells.

M7Q3 · A2. What are spare cells, how are they typically distributed, and what limits what you can build from them?

Gemini Answer

Distribution: Sprinkled uniformly across every placement row (or clustered in ECO spare modules) at ~1–3% of standard-cell area, containing a mix of NAND2, NOR2, INV, AOI21/OAI21, MUX2, and pre-stitched SDFF scan flops with inputs tied to TIEHI/TIELO.
Limitations: Fixed physical coordinates (connecting a spare cell $250 μ m$ away adds large RC wire delay and slew degradation), fixed drive strength (X1/X2), limited flip-flop count, and fixed reset polarity on spare flops.

GPT Answer

Spare cells are preplaced uncommitted gates/flops spread across likely ECO regions. Cell types, drive strengths, location, power domain, legal pin access, and available metal routes limit the patch; a spare flop is not automatically scan/reset compatible.

Claude Answer

Pre-placed, unused cells (NAND/NOR/INV/AOI/OAI/MUX, DFFs with scan) with inputs
tied, sprinkled uniformly at ~1–3% of area or clustered near risky blocks. Limits: drive
strength, distance (wire delay and slew to reach them), cell-type mix, whether spare flops
are pre-stitched into scan with reset connected, and routing congestion around them.

M7Q4 · A3. LEC in one sentence: what does it compare, and what does it not prove?

Gemini Answer

One sentence: LEC mathematically proves whether the combinational Boolean functions driving every mapped pair of key points (flip-flops, latches, primary outputs, black-box inputs) in the Golden and Revised designs are identical for all input combinations—it does not prove functional spec correctness, timing closure (setup/hold), CDC safety, or transient glitch immunity.

GPT Answer

LEC proves corresponding implementations equivalent under the modeled states/modes/assumptions. It does not prove spec correctness, timing, analog CDC behavior, DFT coverage, or correctness of excluded/black-boxed logic.

Claude Answer

It proves the combinational cones between corresponding key points of two designs
are logically identical. It does not prove either design is functionally correct, nor
timing, nor X or reset behaviour.

M7Q5 · A4. Define key points. Name the five kinds of key points Conformal reports and the typical reasons each ends up unmapped.

Gemini Answer

Primary Inputs (PI) / Primary Outputs (PO): Unmapped if port names changed or buses were flattened/ungrouped.
D Flip-Flops (DFF): Unmapped due to synthesis register replication, constant-0/1 flop removal, merging of duplicate flops, retiming, or hierarchy renaming.
DLAT (Transparent Latches): Unmapped if unintended latch was inferred in RTL or an ICG latch wasn't modeled with -clock_gate.
Black Boxes (BBOX — SRAMs, Analog Macros): Unmapped if instance or wrapper hierarchy names differ or macro library models are missing.
Cut Points / Tie-Z / Error gates (Z): Artificial break-points inserted by Conformal to break combinational loops or partition massive multiplier cones.

GPT Answer

Think primary inputs, primary outputs, DFFs, latches, and black-box boundaries. Renaming/elimination can unmap ports; retiming/merging/reset/encoding changes can unmap state; differing macro models or boundary definitions can unmap black boxes. Check the tool version's actual report categories; not every unmapped point is a functional failure.

Claude Answer

Key points: primary inputs, primary outputs, D flip-flops, latches, black boxes
(plus cut points and tie constants). Unmapped because: names changed by ungroup/rename,
constant registers removed, equivalent flops merged, retiming moved flops, phase-inverted
flops, extra scan/test/clock-gating logic, black-box pin mismatch.

M7Q6 · A5. A key point is reported non-equivalent. Walk me through the first three things you do in the tool.

Gemini Answer

Check for Unmapped Key Points in the support cone (report_unmapped_points): 90% of non-equivalences are caused by an upstream unmapped/renamed flop or missing .svf phase inversion/constant-reg mapping, not a real logic bug!
Inspect the Counter-Example Pattern (diagnose / schematic viewer): View the exact input/flop bit values Conformal found where Golden != Revised (e.g., check if scan_en = 1 or test_mode = 1 caused the mismatch because a pin constraint was forgotten!).
Back-trace the schematic cone from the failing D pin to the first diverging internal net using Conformal's automatic fault diagnosis markers.

GPT Answer

Inspect point classification and compare-cone/counterexample; trace to the first differing input/state/control; check reset, scan/test mode, constants, and library modeling before assuming an RTL bug. Reproduce after any setup correction, and never add an assumption solely to hide a mismatch.

Claude Answer

(1) Check the supporting key points of that cone: unmapped or extra support is a
mapping problem, not a bug. (2) Diagnose: compare the two cones' support sets and pull the
failing pattern. (3) Trace that pattern through both cones in the schematic to the first
diverging gate, and check it isn't a missing constraint (scan_en, test mode, undriven pin)
before calling it functional.

M7Q7 · A6. Name four synthesis transformations that make RTL-to-gate LEC fail or need special setup, and the setup for each.

Gemini Answer

DFT Scan Insertion & Test Logic: Add add_pin_constraints 0 scan_en -revised and add_pin_constraints 0 test_mode -revised (and add_ignored_outputs scan_out*).
Clock Gating (ICG insertion): Enable set_flatten_model -gated_clock so Conformal collapses the ICG latch + clock AND gate back into a synchronous D-enable mux on the flip-flops.
Constant & Merged/Inverted Flip-Flops: Enable set_flatten_model -seq_constant -seq_merge and read the synthesis .svf file (read_svf) so inverted-phase flops ( $\overset{―}{Q}$ ) and constant-tied registers map automatically.
Auto-Ungrouping / Datapath Architecture Optimization: Read the .svf file and run analyze_datapath before compare.

GPT Answer

Retiming needs supported sequential/retiming-aware comparison; FSM re-encoding needs state mapping; clock gating needs recognized ICG models and correct test settings; scan insertion needs consistent functional scan-mode constraints and cell models. Flattening, constant propagation, and memory mapping also affect partition/matching setup.

Claude Answer

Retiming → sequential equivalence or disable it. FSM re-encoding → disable or
supply the state mapping. Constant-register removal → enable sequential-constant analysis.
Phase inversion → phase mapping. Datapath re-architecture (Booth, carry-save) → datapath
analysis options. Clock-gating insertion → ICG modelling. Scan insertion → constrain
scan_en = 0.

M7Q8 · A7. Gate-to-gate LEC after a hand ECO: what is the golden, what is the revised, and what do you do about the key points you intentionally changed?

Gemini Answer

Golden: Pre-ECO gate-level netlist. Revised: Post-ECO gate-level netlist.
Handling intentionally changed key points: Run a full compare first and verify that only the exact target flip-flops/outputs listed in the ECO specification fail (Non-Equivalent), while 100% of all other key points pass (Equivalent). Then, swap Golden to the updated RTL (or a small Golden ECO patch module) to prove the modified key points are 100% Equivalent to the intended fix.

GPT Answer

Old-versus-patched gates intentionally differ in the ECO cone. Prove unchanged regions against the old netlist with narrowly documented changed boundaries; prove the entire patched design against corrected RTL. Alternatively construct an independently reviewed corrected golden gate model. Never mark an expected mismatch equivalent or broadly ignore the changed outputs.

Claude Answer

Golden = signed pre-ECO netlist, revised = post-ECO netlist. The cones you changed
are expected non-equivalent: list them before the run, prove them separately against the
new RTL (or a cone-level RTL reference), and require everything else equivalent. "Nothing
else changed" is the main result.

M7Q9 · A8. How does an ECO interact with scan chains? What must you check if you add a flop? If you remove one?

Gemini Answer

Adding a flop: Must use a spare SDFF (not a non-scan DFF), wire its SE to the block's scan_en net, splice its SI and Q (SO) into an existing scan chain in the same clock domain (respecting lockup latches), and update the .spf/.stil scan chain order file for ATPG.
Removing/bypassing a flop: Must short its SI to its SO connectivity so the scan chain is not broken open!

GPT Answer

Added flops require scan membership, reset/clock/test compatibility, chain reconnection, ATPG, and implementation checks; removed flops require chain repair and pattern regeneration as appropriate. Combinational ECOs can preserve chain topology but still affect coverage and patterns.

Claude Answer

Add a flop: it must sit on a chain (pre-stitched spare, or stitch via metal), scan
order file updated, hold checked on the shift path, ATPG regenerated. Remove a flop: bypass
it in the chain, update the order, ATPG again. Both: check clock, reset and the chain length
in the test spec.

M7Q10 · A9. You change a flop's D-input cone with an ECO. What happens to the SDC, the timing sign-off, and DFT ATPG patterns?

Gemini Answer

SDC: Usually unchanged unless a multicycle/false-path exception referenced a deleted internal gate/pin name.
STA: Incremental parasitic extraction (SPEF) and full multi-corner STA must be re-run to verify setup/hold/slew on the newly routed spare cells and any disturbed neighbor wires.
DFT ATPG: Because the combinational logic cone changed, existing ATPG test patterns will compute wrong expected responses—ATPG patterns must be regenerated (or incrementally topped up) and re-simulated in GLS.

GPT Answer

Recheck all new and existing timing paths/corners/modes; update SDC only if the actual timing intent changes. Rerun DFT rules and ATPG/fault simulation as required because the functional cone changed even if scan topology did not.

Claude Answer

SDC unchanged unless an exception names a net or pin in that cone. STA re-run at
all corners for the new cone and wires. ATPG patterns regenerated because the fault list
changed, and pattern simulation repeated.

M7Q11 · A10. Hierarchical vs. flat LEC: when is each used, and what is a "black box" in this context?

Gemini Answer

Hierarchical LEC: Verifies sub-blocks bottom-up one module at a time; once sub_block_A passes LEC, it is declared a black box (add_black_box sub_block_A) when verifying the top-level parent, where Conformal only checks that the pins driving sub_block_A match.
Flat LEC: Dissolves all hierarchy and compares the entire block/chip at once; required when boundary optimization (compile_ultra -autoungroup) moved logic across module ports.

GPT Answer

Hierarchical LEC scales through boundaries but needs sound boundary contracts/matching. Flat LEC sees cross-boundary logic at larger runtime/memory cost. A black box excludes its internal logic from proof and compares only its modeled interface behavior; mismatched or excessive black boxing weakens coverage.

Claude Answer

Hierarchical: sub-blocks verified separately and black-boxed at the parent, when
hierarchy was preserved. Flat: final sign-off, or when ungroup/boundary optimisation crossed
hierarchy. A black box is a module whose internals aren't compared, only its pins mapped,
with equivalence assumed from another run.

M7Q12 · A11. What goes into an RTL release package to SoC integration? List at least eight items and name the consumer of each.

Gemini Answer

Synthesizable RTL filelist (.f) + immutable Git Tag / SHA → SoC Integration / Synthesis / DV
Block-level SDC timing constraints (.sdc) → Synthesis & Physical Design / STA
Power intent file (.upf) → Low-Power Synthesis / PD / Formal UPF
Register description (.rdl / .ipxact / C header files) → Firmware / Driver / SoC DV
Clean Lint + CDC/RDC sign-off reports + approved waiver files → Methodology / SoC Sign-off Lead
Memory macro list + MBIST/wrapper configurations → DFT & Floorplan PD
Integration Guide (clock/reset requirements, strap pins, interrupt list, latency budgets) → SoC Architect & Integrator
Block-level interface SVA bind files → SoC-level Verification (DV)

GPT Answer

Release package: version manifest/hash (everyone), RTL/file list/parameters (integration), interfaces/register map (SoC/SW/DV), SDC and exceptions (STA/PD), UPF (low-power integration), lint/CDC/RDC reports and waivers (signoff), verification plan/results/known bugs (DV), LEC reports/setup (implementation), DFT/test requirements (DFT), macro/library dependencies (PD), and change log/ECO reconciliation (release owners).

Claude Answer

RTL filelist + tag (integration); SDC (PD/STA); UPF (PD/power); lint/CDC/RDC
reports with waivers (methodology); integration guide + register map (SW/FW, integrator);
SVA bind files (DV); DFT spec: scan ports, test modes, MBIST (DFT); synthesis scripts and
constraints (PD); memory/macro list (PD/DFT); verification summary + coverage (DV lead);
release notes / known issues (everyone); LEC report if a netlist ships.

M7Q13 · A12. The same bug is fixed by an ECO in the netlist and "later" in RTL. What process guarantees the RTL fix is equivalent to the ECO, and what happens if someone forgets?

Gemini Answer

Make it a mandatory tapeout close-out gate to merge the corresponding RTL fix into the trunk branch and run an automated RTL-to-Final-Taped-Out-Netlist LEC job that must report 0 Non-Equivalent points. If someone forgets, the next derivative chip starts from stale RTL and silently re-introduces the certification-blocking silicon bug!

GPT Answer

Tie bug, RTL commit, patched-netlist hash, physical ECO, and proof reports in one tracked change. Make corrected-RTL-to-final-gate equivalence a release gate and carry a regression test into the next branch. Otherwise the next synthesis can reintroduce the taped-out bug.

Claude Answer

The ECO log carries the RTL diff, and merging the RTL fix requires an LEC run of
RTL vs the taped-out netlist tag, enforced in CI. If someone forgets, the next generation
inherits RTL that doesn't match silicon: the bug returns, or sim/FPGA stop representing the
chip and nobody notices until certification.

M7Q14 · A13. Constant-propagated or dangling logic: why can an ECO that touches "dead" logic break LEC in a confusing way?

Gemini Answer

Synthesis may have used a "dangling" or constant-0 net to simplify downstream Boolean gates via don't-care optimization, or merged two registers that only behaved identically when that enable was 0. Re-activating it in the netlist invalidates register merging assumptions and causes mysterious key-point mapping failures.

GPT Answer

A supposedly dead signal may be constrained constant or optimized away in one model but reactivated by the patch. Review observability, mode assumptions, tie-offs, and constant propagation before deciding that an unmapped/mismatching cone is harmless.

Claude Answer

Synthesis already removed or merged that "dead" logic, so the golden cone lacks
it; the ECO reintroduces or modifies it, and the revised cone now has different support.
LEC reports unmapped or non-equivalent points that look like a functional bug but are
really the tool having proved that logic constant before you touched it.

M7Q15 · A14. How do you size an ECO before committing: what three numbers do you give the PD lead?

Gemini Answer

Spare cell count & types needed, plus their bounding-box coordinates/hierarchy (e.g., "1 AOI21 + 0 flops within $30 μ m$ of U_ff_txabort").
Total number of modified/new nets and whether any cross hierarchy or long distances (e.g., "3 local nets + 1 tap from U_ff_mumode.Q $180 μ m$ away").
Estimated logic depth / timing slack impact on the affected path (e.g., "0 gates added to critical cca_busy leg; 1 AOI21 delay added to quasi-static mu_mode leg").

GPT Answer

Give incremental cell/spare usage, estimated worst added delay/slack impact, and physical footprint/routing reach. Include wire distance/fanout and schedule confidence; use extracted timing before committing final closure.

Claude Answer

Cells (spares consumed by type), nets cut/added and routes touched (with layers),
and the worst-case timing impact (added depth on which path, estimated slack). Plus the
re-run time for sign-off.

Part B — Deep dive: a hand gate-level ECO (0:20–0:55)

Post-RTL-freeze bug: the Tx abort logic in a MAC block asserts tx_abort when
cca_busy && !tx_active, but the spec change (post-freeze, certification blocker) requires
that in MU mode (mu_mode == 1) the abort also be suppressed while a trigger-based
response is pending (tb_pending == 1).

Current RTL (frozen):
assign tx_abort_d = cca_busy & ~tx_active;
always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) tx_abort_q <= 1'b0;
  else        tx_abort_q <= tx_abort_d;
Required RTL:
assign tx_abort_d = cca_busy & ~tx_active & ~(mu_mode & tb_pending);
Netlist excerpt (post-synthesis, post-DFT, placed):
INVX1   U_inv_txact   (.A(tx_active),  .Y(n_txact_b));
AND2X2  U_and_abort   (.A(cca_busy),   .B(n_txact_b), .Y(tx_abort_d));
SDFFRX1 U_ff_txabort  (.D(tx_abort_d), .SI(scan_in_7), .SE(scan_en), .CK(clk),
                       .RN(rst_n), .Q(tx_abort_q), .QN());
// mu_mode and tb_pending exist as nets: mu_mode is the Q of U_ff_mumode (register
// block, 180 um away); tb_pending is the Q of U_ff_tbpend (same hierarchy, 20 um away).
Spare cells available within 30 µm: SPARE_NAND2X1 ×2, SPARE_INVX1 ×3,
SPARE_AOI21X1 ×1, SPARE_NOR2X1 ×1, SPARE_DFF ×1. Metal-only ECO is required (no
new base-layer cells).

M7Q16 · B1. Design the patch.

(10 min) Design the patch. Using only the spare cells listed, implement the new
function with the minimum number of cells and the minimum impact on the existing timing
path from cca_busy. Write the new netlist lines and state which existing connections
you cut. (Hint: AOI21 gives you ~((A·B) + C) in one cell — think about what you can
fold.)

Gemini Answer

Task 1: Minimum-Cell Patch Design (Protecting Critical `cca_busy` Timing)

Boolean algebra factorization:
- Original: tx_abort_d = cca_busy & ~tx_active
- Required: tx_abort_d = cca_busy & ~tx_active & ~(mu_mode & tb_pending)
- By De Morgan's Law: $\overset{―}{tx_active} \cdot \overset{―}{(mu_mode \cdot tb_pending)} = \overset{―}{tx_active + (mu_mode \cdot tb_pending)} = AOI21 (A = mu_mode, B = tb_pending, C = tx_active)$
Why this is optimal: It uses only 1 spare cell (SPARE_AOI21X1) and keeps cca_busy on its original single AND2X2 gate (U_and_abort.A), adding zero extra gate stages to the fast cca_busy input!

Exact Netlist Changes:

Cut: Disconnect U_and_abort.B from n_txact_b (leave U_inv_txact in place so any other fanout on n_txact_b is undisturbed; if n_txact_b has no other fanout, it safely floats). Disconnect SPARE_AOI21X1 inputs from tie-cells.

Add / Rewire:

// Reuse 1 spare AOI21X1 cell: Y = ~((A & B) + C)
SPARE_AOI21X1 U_eco_aoi (
  .A (mu_mode),
  .B (tb_pending),
  .C (tx_active),
  .Y (n_eco_abort_mask)
);

// Existing AND2X2: only pin .B changes from n_txact_b to n_eco_abort_mask
AND2X2 U_and_abort (
  .A (cca_busy),
  .B (n_eco_abort_mask),
  .Y (tx_abort_d)
);

GPT Answer

Required function is cca_busy & ~(tx_active | (mu_mode & tb_pending)).

Use one spare AOI21 to produce the combined suppression term, then reuse the existing AND. This adds one cell and no extra logic level on the cca_busy input compared with the old path. Confirm actual library pin names, polarity, drive, and metal-only routing legality.

// Reconnect one placed SPARE_AOI21X1; schematic pin names are illustrative.
AOI21X1 U_spare_suppress (
  .A(mu_mode), .B(tb_pending), .C(tx_active), .Y(abort_allowed)
);
// Cut U_and_abort.B from n_txact_b and reconnect to abort_allowed.
AND2X2 U_and_abort (
  .A(cca_busy), .B(abort_allowed), .Y(tx_abort_d)
);
// U_ff_txabort, including SI/SE/CK/RN, is unchanged.
// Leave the old inverter disconnected from this cone; handle its unused output
// and all unused spare pins according to physical tie-off rules.

One additional spare is minimal when retaining the existing AND: the original suppression term must now depend on two more inputs, and AOI21 implements exactly that three-input term. This is a logical mapping claim; placement/extraction still decide feasibility.

Claude Answer

Target: tx_abort_d = cca_busy & ~tx_active & ~(mu_mode & tb_pending).
Fold the two inverted terms: ~tx_active & ~(mu_mode & tb_pending) = ~((mu_mode & tb_pending) | tx_active)
= AOI21(A=mu_mode, B=tb_pending, C=tx_active). One cell.

// cut: U_and_abort.B  <--  n_txact_b
SPARE_AOI21X1 U_eco_aoi   (.A(mu_mode), .B(tb_pending), .C(tx_active), .Y(n_eco_gate));
AND2X2        U_and_abort (.A(cca_busy), .B(n_eco_gate), .Y(tx_abort_d));

U_inv_txact is left as is if n_txact_b has other loads; otherwise its output dangles
(no base-layer change, lint note in the ECO log). cca_busy keeps its single-AND2 depth.

M7Q17 · B2. Alternatives.

(5 min) Alternatives. Give at least one other mapping and explain why yours is better
(cell count, logic depth on the critical input, wire length to mu_mode).

Gemini Answer

Task 2: Alternative Mapping & Why `AOI21` Wins

Alternative (2 cells: SPARE_NAND2X1 + SPARE_NAND2X1 + SPARE_INVX1):
- NAND2(mu_mode, tb_pending) -> n_mu_tb_n
- NAND2(tx_abort_d_orig, n_mu_tb_n) -> INV -> D
- Why AOI21 is superior: The alternative uses 3 spare cells instead of 1, and puts two extra gate delays directly in series with the timing-critical cca_busy path (U_and_abort.Y -> NAND2 -> INV -> U_ff_txabort.D), whereas the AOI21 solution puts the new gate on the parallel tx_active side-branch!

GPT Answer

Generate allow=~(mu_mode & tb_pending) with NAND2, NAND it with old tx_abort_d, then invert into the flop D. Three spare cells, and two additional gate levels on the old critical abort path. It may help placement in a different spare layout, but the AOI21 solution is smaller and preserves the cca_busy logic depth. Keep the same output net naming unambiguous when editing.

Claude Answer

NAND2(mu_mode, tb_pending) → NAND2(tx_abort_d_old, n1) → INV: three cells, two extra
levels on the cca_busy critical path.
NOR2(tx_active, mu&tb) needs an AND = NAND + INV: three cells, one level on tx_active.
Mine: one cell, zero added depth on cca_busy, and the slow 180 µm mu_mode net lands on
an AOI input off the critical path.

M7Q18 · B3. LEC.

(10 min) LEC. Set up the gate-to-gate LEC: what are golden and revised, which key
points do you expect to map automatically, what do you do about the new key point(s),
and what report proves the ECO did only what you intended? Then set up RTL-to-gate LEC
against the updated RTL: what, if anything, is different about this run versus the
original synthesis sign-off?

Gemini Answer

Task 3: Gate-to-Gate & RTL-to-Gate LEC Setup

Gate-to-Gate LEC (pre_eco.v vs. post_eco.v):
- Conformal maps 100% of flops by exact instance name (U_ff_txabort, etc.).
- Run compare: confirm U_ff_txabort is the ONLY Non-Equivalent key point in the entire netlist.
- Run diagnose U_ff_txabort: confirm the counter-example is strictly cca_busy=1, tx_active=0, mu_mode=1, tb_pending=1 (Golden=1, Revised=0).
RTL-to-Gate LEC (updated_rtl.sv vs. post_eco.v):
- Apply standard sign-off constraints (add_pin_constraints 0 scan_en -revised, read_svf, set_flatten_model -gated_clock).
- What is different from original synthesis sign-off: If mu_mode came from another hierarchy module (u_reg_blk.U_ff_mumode.Q) and was wired across hierarchy by an ECO script, hierarchical LEC on the sub-block alone would see a new port; running LEC at the parent/MAC level (where both u_reg_blk and the Tx abort block reside) resolves the key point U_ff_mumode seamlessly and yields 100% Equivalent.

GPT Answer

Elaborate matching library/scan/reset models and functional-mode assumptions. Most existing ports/state should map; a new combinational net is not automatically a new sequential key point.
Old golden gates versus patched gates should expose the intended tx_abort_q cone difference. Prove unaffected logic with precise changed-boundary accounting, and inspect fanout so the new controls do not affect unrelated outputs.
Corrected golden RTL versus patched post-DFT gates must pass for all modeled functional behavior. Preserve scan constraints and async-reset polarity/modeling. There is no permission to exclude the corrected output from this proof.
Required evidence: all compared points equivalent, mapped/unmapped and aborted-point disposition, checked assumptions/black boxes, localized structural diff, and specification-directed tests covering all control combinations. An overall PASS with excluded essential logic is insufficient.

Claude Answer

Gate-to-gate: golden = pre-ECO signed netlist, revised = post-ECO. All flops and POs map
by name; no new key points because no flop was added; the spare's pins are not key
points. Expected non-equivalent set = {U_ff_txabort}. The report that proves intent:
non-equivalent list exactly equals that one point, with everything else equivalent, plus
a cone-level check of U_ff_txabort.D against the new expression.
RTL-to-gate against the updated RTL: same setup as the original sign-off (scan_en = 0,
ICG modelling, test modes constrained). Differences: make sure spare cells aren't
excluded or black-boxed by the original scripts, that mu_mode crossing hierarchy from
the register block is visible (feedthrough port added if the ECO crossed a boundary;
otherwise run flat), and that the dangling inverter doesn't trip an "unused logic"
mismatch. Expect fully equivalent.

M7Q19 · B4. Timing and DFT.

(5 min) Timing and DFT. mu_mode comes from 180 µm away: what is the risk, and how
would you make it a non-issue in your mapping? Does your ECO change the scan chain? What
about if you had needed the SPARE_DFF?

Gemini Answer

Task 4: Timing Risk on the $180 μ m$ `mu_mode` Wire & DFT Scan Impact

Timing & Slew Risk ( $180 μ m$ wire):
- Routing $180 μ m$ in lower/mid metal layers adds $\sim 30 – 45 fF$ of wire capacitance and RC delay, which could cause a max_transition (slew) violation on U_ff_mumode.Q or overload U_ff_mumode if it is a weak X1 flop.
- Mitigation: Put mu_mode on the fastest input pin of SPARE_AOI21X1 (closest to the output stage), and if U_ff_mumode.Q slew is tight, use two of the three available SPARE_INVX1 cells as a non-inverting repeater buffer pair mid-way along the $180 μ m$ route!
Scan Chain Impact:
- Zero scan chain impact because no flip-flop was added or removed (only combinational cone tx_abort_d changed; ATPG patterns simply get re-simulated/topped up).
- If we had used SPARE_DFF: We would have had to connect its .CK(clk), .RN(rst_n), .SE(scan_en), splice .SI and .Q into the local scan chain (unless pre-stitched), and deliver an updated .def + .spf scan-chain order file to the DFT team.

GPT Answer

The 180 um mu_mode connection introduces routing capacitance, slew, and a new timed path through AOI21/AND. Place/use the existing spare near the endpoint, choose the appropriate gate pin arc, and check extracted timing; buffer with remaining compatible spares if necessary. No Boolean mapping makes wire delay irrelevant. Treat mode as false/multicycle only with a real protocol proof, never to ease closure.

No flop changes means scan chain topology stays unchanged, but rerun affected DFT/ATPG checks. Using SPARE_DFF would require verifying its scan/reset/power compatibility, inserting it into a legal chain or an approved alternative test structure, and regenerating test collateral.

Claude Answer

mu_mode 180 µm into an X1 AOI: slew/max-transition risk and a new path
U_ff_mumode → U_ff_txabort. mu_mode is a mode register: declare it quasi-static with
a multicycle/false path backed by an SVA that it only changes while Tx is idle. If it isn't
static, use two spare INVs as a buffer pair near the receiver to fix slew (they can't fix
the wire delay, only the edge).
Scan: unchanged, no flop added. If the SPARE_DFF had been needed: confirm it's
pre-stitched into a chain with reset and clock connected; otherwise stitch SI/SO by metal,
update the scan order file, check hold on the shift path, verify its functional reset
value, and regenerate ATPG.

M7Q20 · B5. Process.

(5 min) Process. List the sign-off artefacts for this ECO: what gets re-run, who
approves, what gets written into the ECO log, and how you ensure the RTL fix lands in the
next generation with LEC proving the RTL matches the taped-out netlist.

Gemini Answer

Task 5: Sign-Off Artefacts & Process Discipline

Artefacts & Re-runs:
- Gate-to-Gate LEC report (1 expected diff) + Updated-RTL-to-Gate LEC report (100% pass).
- Incremental P&R + Metal DRC / LVS / Antenna clean report.
- Incremental SPEF extraction + Multi-Corner Multi-Mode (MCMM) PrimeTime STA report (setup, hold, max_tran, max_cap).
- Incremental ATPG fault coverage check + Gate-Level Simulation (GLS) of the failing MU-trigger abort test.
Close-Out: Commit the 1-line RTL change to the trunk branch tagged with the ECO ID, and lock in a CI LEC check comparing trunk RTL == taped_out_post_eco.v.

GPT Answer

Track bug/spec, approved truth table, RTL commit, old/new netlist hashes, spare instance/pin rewires, ECO script/physical database, LEC setup/results, targeted regression, STA across modes/corners, extraction, DRC/LVS/connectivity, power-intent checks, and DFT/ATPG disposition. Design/DV/PD/STA/DFT and release owners sign their areas. Re-prove the final routed netlist against corrected RTL and merge/backport the RTL fix with a regression so the next generation inherits it.

Claude Answer

ECO log: bug/cert ID, spec reference, RTL diff, netlist diff/ECO script, spare cells
consumed by type, nets cut/added, timing estimate. Re-run: gate-to-gate LEC, RTL-to-gate
LEC with the updated RTL, STA all corners (new mu_mode path), DRC/LVS on metal layers, GLS
with SDF of the failing certification test, ATPG if scan was touched, lint on the RTL.
Approvals: design owner, DV lead, PD lead, DFT if scan, release manager. RTL fix merged
with the ECO ID in the commit, and a CI LEC job of RTL vs the tapeout netlist tag that
must pass before the next-generation branch is cut.

Part C — Your questions (0:55–1:00)

M7Q21 · Questions for the interviewer

Gemini Answer

"Do you use automated functional ECO tools (like Conformal ECO Designer or Fusion Compiler ECO) to generate spare-cell patches first, or do designers craft small patches by hand?"
"How are spare cells structured here—are spare flip-flops pre-stitched into the scan chains during initial DFT insertion?"
"What is the process after tapeout to guarantee every late netlist ECO is reconciled back into the main RTL branch?"

GPT Answer

How are spare resources tracked? Who owns the final routed-netlist proof? What prevents an unreconciled ECO from entering the next RTL release?

Claude Answer

How are spare cells budgeted and placed, and who decides the mix per block?
Is there an automated functional-ECO flow (Conformal ECO) or is it all manual?
Who signs the RTL–netlist reconciliation after tapeout, and is it gated in CI?

Additional notes

Notes. Material not tied to a question

Gemini Answer

No answer in gemini_answer.md.

GPT Answer

Reference

Cadence Conformal ECO Designer describes the role of equivalence checking during ECO analysis and final implementation signoff. Exact commands and report categories must match the installed version.

Claude Answer

No answer in claude_answer.md.

Round 07 — Combined answers (Gemini · GPT · Claude)

Contents

0. Resume probe

M7Q1 · "Three post-freeze ECOs: tell me about the one you were least sure of, and how LEC convinced you."

Gemini Answer

GPT Answer

Claude Answer

Part A — Rapid-fire Q and A (0:05–0:20)

M7Q2 · A1. Functional ECO vs. timing ECO vs. metal-only ECO: who initiates each, and what changes in which files (RTL, netlist, DEF, SDC)?

Gemini Answer

GPT Answer

Claude Answer

M7Q3 · A2. What are spare cells, how are they typically distributed, and what limits what you can build from them?

Gemini Answer

GPT Answer

Claude Answer

M7Q4 · A3. LEC in one sentence: what does it compare, and what does it not prove?

Gemini Answer

GPT Answer

Claude Answer

M7Q5 · A4. Define key points. Name the five kinds of key points Conformal reports and the typical reasons each ends up unmapped.

Gemini Answer

GPT Answer

Claude Answer

M7Q6 · A5. A key point is reported non-equivalent. Walk me through the first three things you do in the tool.

Gemini Answer

GPT Answer

Claude Answer

M7Q7 · A6. Name four synthesis transformations that make RTL-to-gate LEC fail or need special setup, and the setup for each.

Gemini Answer

GPT Answer

Claude Answer

M7Q8 · A7. Gate-to-gate LEC after a hand ECO: what is the golden, what is the revised, and what do you do about the key points you intentionally changed?

Gemini Answer

GPT Answer

Claude Answer

M7Q9 · A8. How does an ECO interact with scan chains? What must you check if you add a flop? If you remove one?

Gemini Answer

GPT Answer

Claude Answer

M7Q10 · A9. You change a flop's D-input cone with an ECO. What happens to the SDC, the timing sign-off, and DFT ATPG patterns?

Gemini Answer

GPT Answer

Claude Answer

M7Q11 · A10. Hierarchical vs. flat LEC: when is each used, and what is a "black box" in this context?

Gemini Answer

GPT Answer

Claude Answer

M7Q12 · A11. What goes into an RTL release package to SoC integration? List at least eight items and name the consumer of each.

Gemini Answer

GPT Answer

Claude Answer

M7Q13 · A12. The same bug is fixed by an ECO in the netlist and "later" in RTL. What process guarantees the RTL fix is equivalent to the ECO, and what happens if someone forgets?

Gemini Answer

GPT Answer

Claude Answer

M7Q14 · A13. Constant-propagated or dangling logic: why can an ECO that touches "dead" logic break LEC in a confusing way?

Gemini Answer

GPT Answer

Claude Answer

M7Q15 · A14. How do you size an ECO before committing: what three numbers do you give the PD lead?

Gemini Answer

GPT Answer

Claude Answer

Part B — Deep dive: a hand gate-level ECO (0:20–0:55)

M7Q16 · B1. Design the patch.

Gemini Answer

Task 1: Minimum-Cell Patch Design (Protecting Critical cca_busy Timing)

GPT Answer

Claude Answer

M7Q17 · B2. Alternatives.

Gemini Answer

Task 2: Alternative Mapping & Why AOI21 Wins

GPT Answer

Claude Answer

M7Q18 · B3. LEC.

Gemini Answer

Task 3: Gate-to-Gate & RTL-to-Gate LEC Setup

GPT Answer

Claude Answer

Task 1: Minimum-Cell Patch Design (Protecting Critical `cca_busy` Timing)

Task 2: Alternative Mapping & Why `AOI21` Wins

Task 4: Timing Risk on the $180 μ m$ `mu_mode` Wire & DFT Scan Impact